p*****r
发帖数: 525 | 1 How can I determine the CIC fitler order to decimate the ADC output.
If we know sigma-delta order, bandwidth and clock rate, Are there any
article to discuss this issues.
Or it relies on the simulation for the anti-alias issues/
Thanks, | c**l
发帖数: 159 | 2 It depends on quantization noise level in DSM output and whether you
decimate to 2 Fs or 4 Fs. You have to run sim to verify your final numbers.
Check the original Hogenauer paper to get a better view of the filter.
【在 p*****r 的大作中提到】
: How can I determine the CIC fitler order to decimate the ADC output.
: If we know sigma-delta order, bandwidth and clock rate, Are there any
: article to discuss this issues.
: Or it relies on the simulation for the anti-alias issues/
: Thanks,
| p*****r
发帖数: 525 | 3 Thanks a lot.
Therefore, you do rely on the simulation. If the decimation rate is higher.
You need cascaded several stages. The combinations will be a large set. Do
we need try and simulate all of them.
It will be great if there is some theoretical analysis article, which can be
a start design point before the sumulation. | c**l
发帖数: 159 | 4 Given the quantization noise level, bandwidth, and final oversampling ratio,
you should have a rough idea of the order of CIC. Once you know the order,
you can try the multi-stage trick to reduce the DC gain of the filter. In
this step, you probably have several cases to simulate to know the exact SNR
coming out.
be
【在 p*****r 的大作中提到】
: Thanks a lot.
: Therefore, you do rely on the simulation. If the decimation rate is higher.
: You need cascaded several stages. The combinations will be a large set. Do
: we need try and simulate all of them.
: It will be great if there is some theoretical analysis article, which can be
: a start design point before the sumulation.
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