p***e
发帖数: 118 | 1 请问DSM的部分
QUANTIZER OUTPUT BIT多跟少的trade off是??
另外有什么资料可以找到比较详细的single loop dsm 是如何implement??
thanks |
d********i
发帖数: 91 | 2 output bit应该和阶数相关
【在 p***e 的大作中提到】
: 请问DSM的部分
: QUANTIZER OUTPUT BIT多跟少的trade off是??
: 另外有什么资料可以找到比较详细的single loop dsm 是如何implement??
: thanks
|
d*****i
发帖数: 27 | 3 single bit is always linear, and multi-bit has nonlinear problem. But multi-
bit can have higher SNR. You can read the book <
Modulation>>. |
p***e
发帖数: 118 | 4 我的理解是3阶可以1 bit 但1阶不能3 bit吧
【在 d********i 的大作中提到】
: output bit应该和阶数相关
|
p***e
发帖数: 118 | 5 Thanks. I think you are referring to SDM ADC. But how about DIGITAL SDM for
pll, which should not have linearity problem since it is all digital?
multi-
【在 d*****i 的大作中提到】
: single bit is always linear, and multi-bit has nonlinear problem. But multi-
: bit can have higher SNR. You can read the book <: Modulation>>.
|
d********i
发帖数: 91 | 6 直观上可不可以这么理解，阶数越大，低高频Q noise就相差越大，需要更多bit去表征
【在 p***e 的大作中提到】
: 我的理解是3阶可以1 bit 但1阶不能3 bit吧
|
d*****i
发帖数: 27 | 7 more bits, more dividers. You can decrease QN by increasing your order.
Write matlab model for it. |
