v******r
发帖数: 69 | 1 what is 阶梯图 in english? step-up / step-down schematics? switching
diagrams? VI sat curve with linear ranges? |
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b*******m
发帖数: 72 | 2 10 年前，Nortel, Lucent, Motorola 如日中天，谁能想到短短十年就被Huawei, ZTE
给灭了。
sorry too slow to type Chinese. back to 80's and 90's, Nortel was not just
designing telephone switch, they also design ASICs which goes to telephone
switch, like echo cancellation, SDH framer, CPU chipset(similar to north and
south bridge), and they work with chip maker(like Motorola semiconductor
group) to shrink their system to a IC(like 68360, PowerQUICC)
They are not only designing ASICs, they also design EDA tools, like
schemat |
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a******e
发帖数: 80 | 3 代人发帖，请指教，谢谢
我有一个数字设计，是在Cadence Virtuoso里用foundry提供的standard digital
cells建的 schematic，然后用"Virtuoso verilog environment for NC-Verilog"生成
verilog网表。在这个网表里，这些digital cell的连接是按端口的位置对应连接, 而
不是用端口名对应连接,比如:
NO2X1 I70 ( nQ, SET, Q);
NO2X1 I71 ( Q, nQ, RESET);
注： NO2X1是一个两输入NOR门
将这个网表作为输入文件导入到Encounter时，出现如下错误信息：
**ERROR: (SOCVL-349): Missing module definition in netlist for NO2X1.
**ERROR: (SOCVL-209): [./SR_latch_5V.v:16]: Parser does not handle
connection-by-position for this module.
at ,.
**ER |
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a******e
发帖数: 80 | 4 在cadence里的virtuoso schematic，我记得有一个快捷键，可以highlight出同一net
name的所有wire。但一时记不得是哪个键了，哪位大虾提示一下，谢谢。 |
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a******e
发帖数: 80 | 5 I am using CADENCE Virtuoso Analog Design Environment for simulation . The
simulator opted is AMS. Basically, I have two main blocks to be simulated.
One is written in verilog code and created as a functional view while the
other block is drawn in schematic using foundry's cells. Thus, it is a mixed
-signal simulation and AMS simulator is chosen.
When I simulated the config view of the above circuits, I got thousands of
error messages (all in the same type) in my simulation.log
ncelab: *W,DLCILI |
|
ET
发帖数: 10701 | 6 去edaboard.com去问吧。
very
the |
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a******e
发帖数: 331 | 7 I am not a SOC encounter expert and using Synopsys.
I think SOC Encounter same as other Place & Routing tools, based on
constraints to determine the buffer stages and driving strength. In Design
Compiler, you can set dont touch on the netlist and buffers to keep the
netlists. You can find equivalent command in SOC encounter.
very
the |
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m**********e
发帖数: 57 | 8 I remember that there is an option: do not restructure logic(or similar name
) when you optimize the design. Search SoCE manual, or you can have this
simple question answered with cadence sourcelink. Sorry can not give you
answer, I am away from IC design for 3 years. |
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H****E
发帖数: 444 | 9 1、在Virtuoso Schematic Editor中如何把手写的网表文件导入成一个symbol？
2、通常说的phase是指对于sin(x)还是cos(x)……
求指点，谢谢！ |
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a*m
发帖数: 6253 | 10 Symbol is to identify the pins for the port connectivity.
In your netlist, you need to define the pins for the symbol.
BTW, it is way easier to generate the schematic instead of import your
netlist. Why bother? |
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R*****o
发帖数: 204 | 11 schematic and results please.
你的图挂了，貌似 |
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q*******n
发帖数: 52 | 12 想找个ideal switch model, 要求有控制开关, Ron=0ohm, Roff = infinity ohms. 因
为在一些precision电路中, 希望开关换成理想的, 先算别的部分引进的误差.
在analogLib, 有个model called "switch", 但是open switch resistance, close
switch resistance 必须设成实际的数, 好象设成 0 会出错.
还看到一个model called "sp1tswitch", 这个model 好象没有控制开关, 只有静态的
设置成开或关.
最近问题太多, 感谢本版帮助. |
|
x****g
发帖数: 2000 | 13 任何仿真都是有精度的
你把Ron和Roff设到一个跟你计算精度相近的值不就结了嘛
1G, 1n这些值都可以吧
设成0真的会出错， |
|
ET
发帖数: 10701 | 14 还是先算开关的误差吧。。那东西一般也就是最大的误差。 |
|
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f*********r
发帖数: 674 | 16 台湾有个eda软件很象cadence...
我觉得用schematic capture够了
当然cadence的spectre还是很强的 |
|
l****o
发帖数: 184 | 17 The requirement in the original paper is w(closed loop -3dB frequency)
zero)
it is mentioned that the pole zero doublet should be pushed to even higher
frequency which is equal to the non-dominate pole.
As for the feedback loop,as long as you keep it as a one pole system, it
will not be that a big problem.
My question is which node contributes to the pole in the doublet if we only
see from the schematic.:)
那。
domina
charac |
|
S****e
发帖数: 1063 | 18 It seems like my explaination didn't work well enough, so I will try alittle
harder.
The compensator is NOT a transconductance amplifier. It's normally some form
of intergrator to drive the error to zero. All the control signals shown on
the schematic you provided are voltages. The analog comparator compares
voltages, not current.
The sensed current is converted to a voltage by a sense resistor Rf. The
output of the compensator defines the peak current by turning off the switch
@ Is(t)*Rf = Ic(t |
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n*****a
发帖数: 313 | 19 A good point! That is what I am considering now. But I still can not have a
mature schematic to realize it. |
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d*******l
发帖数: 110 | 20 站内发简历，我会转给那个经理。
》》》》》》》》》》》》》》》
Located at the heart of Telecom Corridor in Richardson, Texas, a fast
growing wireless communication startup is looking for a hardware test intern.
· RESPONSIBILITIES:
· Assemble and test prototype electronic and rf assemblies
· Design wiring harnesses and system cabling
· Check schematic netlists and BOMs
· Coordinate fabrication and turn-key assembly of PCBs with vendors
· Set up and maintain electronics lab
· Design and build test fixtures
· Define tes |
|
I***a
发帖数: 704 | 21 我现在有1个foundry提供的spectre model，描述一个transistor的 ，但是foundry没
有提供cadence里面的cell ，我现在需要做LVS， 就把foundry提供的类似的cell复制
一个新的，然后用TOOLS->CIF->Edit修改了 Base Model Name 和 Model Name 这2个参
数。 但是LVS得到的 schematic的netlist 还是用的修改前的 model name。 如何解决
呢？ |
|
ET
发帖数: 10701 | 22 search "pcell in cadence".
基本原理是： transistor level gate logic (nand, nor, xor, 3-input, etc....)
with schematic, layout, parastic extraction coming with spice model simulat
ion -》 generate timing/power info for those gates (called pcell).
你建了个ic usa group， 然后听起来似乎你啥也不知道， 建这个group为何？ |
|
s*****o
发帖数: 22187 | 23 我是外行，所以想了解一下。我想请问一下，国内自己设计（从画schematic开始，不
考虑抄版的）的芯片占多大比例呢？谢谢 |
|
i*e
发帖数: 56 | 24 Attach your schematics, I will try to help you out.
performance |
|
T******T
发帖数: 3066 | 25 SW apps is actually an interesting position since he/she will be
developing in various customer platforms, RTOS environments.
HW apps is kinda dry in comparison, most of the time is spent testing,
trying to reproduce reliability issues, corner case failures, reviewing
customer platform design schematics etc. |
|
I***a
发帖数: 704 | 26 你要hspice netlist干什么？
如果是为了做LVS，直接把verilog netlist导入Cadence得到schematic，然后用Calibre/Assura做LVS |
|
I***a
发帖数: 704 | 27 Cadence schematic里 一个transistor的 multiplicity
这个参数是起什么作用的 ？ |
|
z****m
发帖数: 5 | 28 Electrical Engineer (Hardware)
– Zyno Medical LLC (Natick, MA)
Zyno Medical LLC is looking for a Hardware Engineer to work on
microprocessor based circuitry for applications in medical devices.
RESPONSIBILITIES:
Your responsibilities include but not limited to the following:
- Hardware design based on system level requirements, including but not
limited to schematic capture, PCB layout, component selection, and assembly
instructions;
- Prototype building, testing, debugging and optimization.
- |
|
T******T
发帖数: 3066 | 29 Ditto, Honestly, pure digital HW is kinda dry after a while.
Countless days are spent review schematics, finding parts, talking to
vendors, reading datasheets, matching net/pin names etc. After a couple of
them, it gets old fast. I think the most interesting part of digital HW
design comes when the spec requirements becomes strict which forces people
to actually focus more on performance rather than just functionality.
Stuff like 100mV of voltage swing margin on a digital SOC core rail with
h |
|
T******T
发帖数: 3066 | 30 In my opinion, 1/2 of HW design is in the detail design specification
stage. That requires a lots of cross-functional team discussions and
communications. Stuff after the schematic could be outsourced and should
be out sourced.
be be |
|
l***g
发帖数: 1035 | 31 exactly... layout should be outsourced.. but ppl here usually worry abut IP
so they don't want to give out the schematic... |
|
I***a
发帖数: 704 | 32 用Calibre extract RC后仿真生成 calibre view
如何在用Ultrasim仿真的时候指定用这个calibre view而不是schematic view呢？
用config吗 ？ |
|
I***a
发帖数: 704 | 33 top-level里有2个instance,
一个给的是spectre netlist,
另一个有schematic,这种情况如何仿真？ |
|
A***J
发帖数: 478 | 34 我做THESIS的时候的方法是，你先要用STANDARD CELL把那些NETLIST的东西CONVERT 成
SCHEMATIC,然后在用SPECTRE 仿真， CADENCE里面有个IMPORRT VERILOG的选项，但是
必须在导入前有STRARD CELL. |
|
O*y
发帖数: 317 | 35 猎头发的。
System Applications Engineer - South Central California - Medical Ultrasound
Circuit Design - Company will relocate
MUST HAVES FOR THIS POSITION:
Systems Applications experience in "Medical Ultrasound Circuit Design" and
Imaging concepts.
Working knowledge of SPICE, Labview, Matlab and C/C++ programming and GUI
design, PC driver development and applications
Familiarity with Schematics, BOM's, low noise, high speed design and layout,
board bring-up and test.
EDUCATION REQUIREMENTS:
Minimum |
|
j******e
发帖数: 1424 | 36 发泄一下， 拍砖建议都欢迎
在一小公司干了6年的board level design, 从archetecture到画schematic 到
prototype bring up. lead了大大小小几十个产品 大到 10 个卡的 Ethernet base
modeler system, 小到 简单的 2口 Ethernet media converter。 最近和老板闹翻想
换工作， 本以为挺好找的， 结果一看原来没几个公司要作board level人的。6年白混
了。。。。。。。。。。 靠。
版上那位有推荐，先谢了， 俺在南加。 |
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j*****e
发帖数: 228 | 37 下周四的面试，关于Pcb design和testing的职位，面试内容是schematic reading,
troubleshooting and soldering.
请各位给些建议，该准备什么 |
|
Q****r
发帖数: 7340 | 38 也就是心理感觉不一样
看看manual，画个schematic图，然后画个封装，布个线
再看一下，布线需要注意什么，就没了
布个双层板根没布没什么区别的 |
|
g******u
发帖数: 3060 | 39 you are in this field and you don't know what to do? weird to me. |
|
r*******n
发帖数: 3020 | 40 It's not necessary for software developer to
know how to design hardware but is necessary
to understand the schematics of design files.
In addition, here is a great resource
http://beagleboard.org/
you maybe find it useful. |
|
c*****3
发帖数: 17 | 41 My agent just sent me a few job openings in 3 states. If you are an EE and
qualified, pls send your cv to my mailbox here. Do not waste your time, if
you do not meet the mini. requirements. If you are successful, I will get
referal bonus. Good luck!
Senior Electrical Engineer (Utility) - Maine
Type: Full-Time
Description: This position will work with, supervise or coordinate the work
of engineers assigned to electrical T&D projects. The list of possible
duties includes those noted below as well ... 阅读全帖 |
|
s*****r
发帖数: 847 | 42 标注一下，我是转贴而已哦
有兴趣的跟flyinmeteor联系哈
【 以下文字转载自 JobHunting 讨论区 】
发信人: flyinmeteor (raindance), 信区: JobHunting
标 题: netlogic opening - physical design engineer in CPU group
发信站: BBS 未名空间站 (Thu Oct 21 02:53:18 2010, 美东)
今天manager突然说可以找fresh grad. 如果觉得fit的话, 跟我联系
This position requires an understanding of RTL to GDS flows, CMOS device
operation and advanced layout rules.
Responsibilities:
Ownership of design floor planning, synthesis, DFT, place and route,
clock and power distribution, static timing an... 阅读全帖 |
|
g*****d
发帖数: 210 | 43 第一次做这方面的CIRCUIT
没什么经验
1GHZ .18um CMOS process
请问DESIGN的重点
是让所有DIFF PAIR 的vdsat做的越小越好吗(say 50mV)
还有pre driver 大小该如何决定
请推荐一下参考资料
有SCHEMATIC最好
thanks a lot.. |
|
I***a
发帖数: 704 | 44 我要用spectre仿真没有layout的schemtic, 但是这个schematic里必须要有clock
buffer,因为clock buffer的功耗必须算进去。
我知道有别的方法可以估计功耗， 但是我们要和另一个设计比较，
必须用这个方法。因为那个设计没有cell characterization, 只能用spectre 仿真得
到功耗. |
|
c****s
发帖数: 2487 | 45 好像这个工艺对gate die-down diode要求比较多啊
那你就加上呗
有的schematic的property里就有tie-down的选项
选中之后就由layout自主了，不过multi power domain的时候很危险。。。 |
|
u*****e
发帖数: 8 | 46 Please PM me a brief bio if interested.
We also have a Signal Integrity application engineering opening based in
China. Experiences are required.
RIMARY PURPOSE:
Responsible for identifying and justifying new product opportunities with
Marketing and Sales. Product development process is “hands-on” and
includes the project management, concept, design, simulation, verification,
analysis, characterization, qualification, to volume production of multi-
gigabit copper transceivers. Will lead a multif... 阅读全帖 |
|
g******u
发帖数: 3060 | 47 I went to some big company interviewes for apps and found some positions are
quite boring, especially in headquarters. There is some title called senior
engineer on low voltage MOSFET app, how complicated is that? But some local office may require apps to design whole system, that's better.
Anyway I'm not optimistic about <100W app engineering, Chinese guys can do
same designs way cheaper. You may end up working hard but the position was
outsourced.
But if you are a full round designer-- design ... 阅读全帖 |
|
s****t
发帖数: 1049 | 48 怎么回事呢，用学校的机器，TA也不懂，在网上看好像是路径设置问题，找不到
licence文档了？要怎么改呢，我刚开始学cadence..
错误信息是 Warning iclic-3 could not get licence virtuoso-Schematic-L |
|
h*******y
发帖数: 896 | 49 If your background matches this position, please send me your resume
(email needed).
========================
Analog and Mixed Signal IC Design Engineer
Job Posting: Jan 24, 2011
Primary Location: US-TX-Austin-Oak Hill (TX30)
Job: Analog and Mixed Signal
Education Level: Bachelor's Degree
Job Type: Experienced
Scope of Responsibilities/Expectations:
Design of analog and mixed signal circuits in advanced CMOS technologies for
automotive and industrial & multi-market applications; including defini... 阅读全帖 |
|
V******B
发帖数: 3940 | 50 你把schematic的图画出来，然后布线好
就把PCB layout的文件发给制版商就可以了，等一到两个星期就可以收到，收费是看板
子的大小，几
层板
google PCB layout 然后查一下review，挑一个review不错的，然后就上那个网站，
upload 文
件，付钱。给网站的representitve打电话，问一下情况 |
|
