z****m
发帖数: 5 | 1 Electrical Engineer (Hardware)
– Zyno Medical LLC (Natick, MA)
Zyno Medical LLC is looking for a Hardware Engineer to work on
microprocessor based circuitry for applications in medical devices.
RESPONSIBILITIES:
Your responsibilities include but not limited to the following:
- Hardware design based on system level requirements, including but not
limited to schematic capture, PCB layout, component selection, and assembly
instructions;
- Prototype building, testing, debugging and optimization.
- |
t********t
发帖数: 5415 | 2 不是挑刺啊，这些要求国内强一点的本科生都能做了，5年经验就直接把我这样的fresh
卡在门外...另外我就是MA的，natick那地方有个巨型mall，生活满爽，还可以和
mathworks套近乎 |
c*******l
发帖数: 4801 | 3 能做和做的好，不出错，是两回事！
fresh
【在 t********t 的大作中提到】
: 不是挑刺啊，这些要求国内强一点的本科生都能做了，5年经验就直接把我这样的fresh
: 卡在门外...另外我就是MA的，natick那地方有个巨型mall，生活满爽，还可以和
: mathworks套近乎
|
g******u
发帖数: 3060 | 4 国内fresh有这么牛？这可是做产品。
要求虽然不算高，可要一人全抗还是真得有经验不可。这个位置要求其实看来还偏软。
fresh
【在 t********t 的大作中提到】
: 不是挑刺啊，这些要求国内强一点的本科生都能做了，5年经验就直接把我这样的fresh
: 卡在门外...另外我就是MA的，natick那地方有个巨型mall，生活满爽，还可以和
: mathworks套近乎
|
l***g
发帖数: 1035 | 5 why don't u try. you might have your chance.
at least you can pass the language requirements.
but i doubt your claim of "sheng huo man shuang" in Natick...
fresh
【在 t********t 的大作中提到】
: 不是挑刺啊，这些要求国内强一点的本科生都能做了，5年经验就直接把我这样的fresh
: 卡在门外...另外我就是MA的，natick那地方有个巨型mall，生活满爽，还可以和
: mathworks套近乎
|
d****o
发帖数: 1112 | 6 嗯，硬件方面其实毫无挑战
【在 g******u 的大作中提到】
: 国内fresh有这么牛？这可是做产品。
: 要求虽然不算高，可要一人全抗还是真得有经验不可。这个位置要求其实看来还偏软。
:
: fresh
|
l***g
发帖数: 1035 | 7 seriously this work should be outsourced. faster, cheaper and may even be be
tter. work in us should focus on sw, certification and reliability.
assembly
【在 z****m 的大作中提到】
: Electrical Engineer (Hardware)
: – Zyno Medical LLC (Natick, MA)
: Zyno Medical LLC is looking for a Hardware Engineer to work on
: microprocessor based circuitry for applications in medical devices.
: RESPONSIBILITIES:
: Your responsibilities include but not limited to the following:
: - Hardware design based on system level requirements, including but not
: limited to schematic capture, PCB layout, component selection, and assembly
: instructions;
: - Prototype building, testing, debugging and optimization.
|
w*******d
发帖数: 3714 | 8 我还觉得要求好高呢，既要会电路设计，又要熟嵌入式，呵呵
fresh
【在 t********t 的大作中提到】
: 不是挑刺啊，这些要求国内强一点的本科生都能做了，5年经验就直接把我这样的fresh
: 卡在门外...另外我就是MA的，natick那地方有个巨型mall，生活满爽，还可以和
: mathworks套近乎
|
w*******d
发帖数: 3714 | 9 natick有minado啊！
【在 l***g 的大作中提到】
: why don't u try. you might have your chance.
: at least you can pass the language requirements.
: but i doubt your claim of "sheng huo man shuang" in Natick...
:
: fresh
|
g******u
发帖数: 3060 | 10 大公司如果有大项目，有钱花很长时间雇一堆人做同一项目那是自然可以outsource。
小工程公司基本都是一二人全做，从硬件到画板到软件到认证等等都要在很短时间搞出
来，那交流就很重要了。
有些美国公司反而把设计部门反搬回美国，只在中国生产，不是不能干活，是交流不顺
，而且现在国内要价也高了。
be
【在 l***g 的大作中提到】
: seriously this work should be outsourced. faster, cheaper and may even be be
: tter. work in us should focus on sw, certification and reliability.
:
: assembly
|
|
|
l***g
发帖数: 1035 | 11 en... and leohmann's next door...
food is ok.. not much to play.. and housing is too expensive.
【在 w*******d 的大作中提到】
: natick有minado啊！
|
c*****n
发帖数: 1877 | 12 感觉大家很看不起硬件工程师啊。我本人以前做过软件，毕业后做硬件工程师3年多了，
没有觉得硬件活有大家想象得那么容易。首先即使是全数字电路，现在的频率比以前高
多了，比如DDR3时钟已经到800MHz,这种频率对硬件设计是个严峻挑战，我绝对不相信新
手能做出这种电路并保证系统稳定。如果电路还包含了模拟特别是射频微波部分，那就
更是难度大了。比如你要保证噪音小，保证失真小，射频接口反射在15dB以下....这种
东西没有几年的经验绝对是做不好的。
【在 d****o 的大作中提到】
: 嗯，硬件方面其实毫无挑战
|
d****o
发帖数: 1112 | 13 我也是做硬件的，并没有瞧不起硬件的意思。
射频微波这个和楼主找的硬件不大一样吧
了，
信新
【在 c*****n 的大作中提到】
: 感觉大家很看不起硬件工程师啊。我本人以前做过软件，毕业后做硬件工程师3年多了，
: 没有觉得硬件活有大家想象得那么容易。首先即使是全数字电路，现在的频率比以前高
: 多了，比如DDR3时钟已经到800MHz,这种频率对硬件设计是个严峻挑战，我绝对不相信新
: 手能做出这种电路并保证系统稳定。如果电路还包含了模拟特别是射频微波部分，那就
: 更是难度大了。比如你要保证噪音小，保证失真小，射频接口反射在15dB以下....这种
: 东西没有几年的经验绝对是做不好的。
|
T******T
发帖数: 3066 | 14 Precisely, just Signal Integrity and Power integrity are challenges enough
in true high speed, high density hardware designs. If you wanna do it right
, there's a fair amount of s-parameter modeling and board level simulation
involved especially if it also involves RF components.
Those plp who think a fresh BS grad would be able to do a good job with a
complex design is obvious not in the field.
了，
信新
【在 c*****n 的大作中提到】
: 感觉大家很看不起硬件工程师啊。我本人以前做过软件，毕业后做硬件工程师3年多了，
: 没有觉得硬件活有大家想象得那么容易。首先即使是全数字电路，现在的频率比以前高
: 多了，比如DDR3时钟已经到800MHz,这种频率对硬件设计是个严峻挑战，我绝对不相信新
: 手能做出这种电路并保证系统稳定。如果电路还包含了模拟特别是射频微波部分，那就
: 更是难度大了。比如你要保证噪音小，保证失真小，射频接口反射在15dB以下....这种
: 东西没有几年的经验绝对是做不好的。
|
g******u
发帖数: 3060 | 15 同意，再简单的硬件电路，如果是刚毕业只看过书没高人带一把，还真的做不对。
软件倒不一样。
right
【在 T******T 的大作中提到】
: Precisely, just Signal Integrity and Power integrity are challenges enough
: in true high speed, high density hardware designs. If you wanna do it right
: , there's a fair amount of s-parameter modeling and board level simulation
: involved especially if it also involves RF components.
: Those plp who think a fresh BS grad would be able to do a good job with a
: complex design is obvious not in the field.
:
: 了，
: 信新
|
d****o
发帖数: 1112 | 16 对啊，光是选器件就搞不定
但是做过几个之后，基本上就没多少悬念了，boring..
【在 g******u 的大作中提到】
: 同意，再简单的硬件电路，如果是刚毕业只看过书没高人带一把，还真的做不对。
: 软件倒不一样。
:
: right
|
T******T
发帖数: 3066 | 17 Ditto, Honestly, pure digital HW is kinda dry after a while.
Countless days are spent review schematics, finding parts, talking to
vendors, reading datasheets, matching net/pin names etc. After a couple of
them, it gets old fast. I think the most interesting part of digital HW
design comes when the spec requirements becomes strict which forces people
to actually focus more on performance rather than just functionality.
Stuff like 100mV of voltage swing margin on a digital SOC core rail with
h
【在 d****o 的大作中提到】
: 对啊，光是选器件就搞不定
: 但是做过几个之后，基本上就没多少悬念了，boring..
|
T******T
发帖数: 3066 | 18 In my opinion, 1/2 of HW design is in the detail design specification
stage. That requires a lots of cross-functional team discussions and
communications. Stuff after the schematic could be outsourced and should
be out sourced.
be be
【在 l***g 的大作中提到】
: seriously this work should be outsourced. faster, cheaper and may even be be
: tter. work in us should focus on sw, certification and reliability.
:
: assembly
|
l***g
发帖数: 1035 | 19 exactly... layout should be outsourced.. but ppl here usually worry abut IP
so they don't want to give out the schematic...
【在 T******T 的大作中提到】
: In my opinion, 1/2 of HW design is in the detail design specification
: stage. That requires a lots of cross-functional team discussions and
: communications. Stuff after the schematic could be outsourced and should
: be out sourced.
:
:
: be be
|
d****o
发帖数: 1112 | 20 there is no pure digital HW.
100mV of voltage swing margin is not hard at all to meet. I have done some d
esigns that uses 1.0V+/-50mV@40A, 0.9V+/-30mV@20A or more, actually my power
distribution design could make sure the core gets +/-3% of nominal voltage.
Why is it so hard?
Also done lot of memory designs, DDR, DDR2, DDR3, QDRII, etc. IOs like 10/10
0/1G/10G ethernet,PCIe,FC etc, X86/PPC/ARM/MIPS... No challenge at all.
By the way, simulation is just a tool, you could end up with garbage in
【在 T******T 的大作中提到】
: In my opinion, 1/2 of HW design is in the detail design specification
: stage. That requires a lots of cross-functional team discussions and
: communications. Stuff after the schematic could be outsourced and should
: be out sourced.
:
:
: be be
|
|
|
d****o
发帖数: 1112 | 21 As a design engineer, you should define correct layout rules then let your
PCB
engineers do their work. Of course you need to review their work carefully. |
T******T
发帖数: 3066 | 22 Good for you man, but those high speed, high load designs weren't so
trouble free for us, so PI simulation did matter in the end. Of course,
if you don't set it up right, everything looks great, but comes out
garbage like you said.
some d
power
voltage.
10/10
all.
in garb
【在 d****o 的大作中提到】
: there is no pure digital HW.
: 100mV of voltage swing margin is not hard at all to meet. I have done some d
: esigns that uses 1.0V+/-50mV@40A, 0.9V+/-30mV@20A or more, actually my power
: distribution design could make sure the core gets +/-3% of nominal voltage.
: Why is it so hard?
: Also done lot of memory designs, DDR, DDR2, DDR3, QDRII, etc. IOs like 10/10
: 0/1G/10G ethernet,PCIe,FC etc, X86/PPC/ARM/MIPS... No challenge at all.
: By the way, simulation is just a tool, you could end up with garbage in
|
T******T
发帖数: 3066 | 23 Yeab, rules and constraints are given as the 1st pass procedure. The
prelim layout is reviewed, extracted into sigrity and ansoft simulation
suites and carefully analyzed for 2nd pass. That's when we sit with the
PCB layout guys to start tweaking things. Many HW guys don't really
believe in the tools and still like to use rule of thumb, and most of the
time, it works out fine for them, but I still prefer a more methodical
process.
your
carefully.
【在 d****o 的大作中提到】
: As a design engineer, you should define correct layout rules then let your
: PCB
: engineers do their work. Of course you need to review their work carefully.
|
d****o
发帖数: 1112 | 24 for this kind of low voltage high current design, I think understanding the
load is very important and then you can figure out your PI plan.
Altera has a very good PI spreadsheet for their device.
【在 T******T 的大作中提到】
: Good for you man, but those high speed, high load designs weren't so
: trouble free for us, so PI simulation did matter in the end. Of course,
: if you don't set it up right, everything looks great, but comes out
: garbage like you said.
:
: some d
: power
: voltage.
: 10/10
: all.
|
d****o
发帖数: 1112 | 25 these tools are very expensive...most of small to medium companies can't aff
ord one. Actually even in big companies, normally they have SI group to pro
vide SI/PI analysis to HW designers.
【在 T******T 的大作中提到】
: Yeab, rules and constraints are given as the 1st pass procedure. The
: prelim layout is reviewed, extracted into sigrity and ansoft simulation
: suites and carefully analyzed for 2nd pass. That's when we sit with the
: PCB layout guys to start tweaking things. Many HW guys don't really
: believe in the tools and still like to use rule of thumb, and most of the
: time, it works out fine for them, but I still prefer a more methodical
: process.
:
: your
: carefully.
|
T******T
发帖数: 3066 | 26 Well, when we are cost crunched to a tiny board with 4 layer routing, 2
ground planes, no power planes, only tiny power traces, high dynamic
current profiles, 2 or 3 high power RF transceivers sitting next to DDR
and CPU, tight ass European spec, there's not much choice but to use those
expensive tools. We did have dedicated SI groups, but it was a big
company and they get busy, so we've gotta do it.
aff
pro
【在 d****o 的大作中提到】
: these tools are very expensive...most of small to medium companies can't aff
: ord one. Actually even in big companies, normally they have SI group to pro
: vide SI/PI analysis to HW designers.
|
d****o
发帖数: 1112 | 27 sounds like apple, hehe.
【在 T******T 的大作中提到】
: Well, when we are cost crunched to a tiny board with 4 layer routing, 2
: ground planes, no power planes, only tiny power traces, high dynamic
: current profiles, 2 or 3 high power RF transceivers sitting next to DDR
: and CPU, tight ass European spec, there's not much choice but to use those
: expensive tools. We did have dedicated SI groups, but it was a big
: company and they get busy, so we've gotta do it.
:
: aff
: pro
|
