a******e
发帖数: 80 | 1 我仿真一个PLL （cadence schematic simulation），里面的VCO的频率取决于它的前
一级的电压。
因为我做的是时域的仿真，所以当我画VCO的输出电压时，得到一个振荡的信号，当然
，频率不是非常固定，
我现在想画出这个振荡信号的频率，可是当我选了Calculator中Special function里的
frequency时，我得到的是一个single value （scalar data），而不是一个随着时间
变化的值。
请问应该怎么做，谢谢。 |
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c*********6
发帖数: 858 | 2 You can export the netlist from the schematics in the Cadence Capture. The
netlist is just a file that shows how the components interconnect. |
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w********u
发帖数: 90 | 4 用的是gilbert cell ，lvs 用assura calibre 都通过的。郁闷了，我昨天吧input DC
blocking cap 从10p 改动到4p ,结果差了5倍，我真怀疑calibre工具的问题了。 |
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w********u
发帖数: 90 | 5 4GHz频率，按理说input resistance 应该是1000的数量级。 |
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a*******e
发帖数: 62 | 6 多谢了 我忽略了 simulation加variation
具体来说是根据工艺把schematic的参数故意调差还是做梦特卡洛分析？ |
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m*******9
发帖数: 13 | 7 你现在的接法不就是已经接在电路中了吗？看不懂LZ想问什么东西。这个是经典的增加
Vbe电压从而减小失配的方法，不过LZ就画了半边电路而已
要钳位的点从Q2 的E极接出去就可 |
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e***b
发帖数: 53 | 8 you are trying to simulate BJT with PMOS model. that is meaningless. |
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x****g
发帖数: 2000 | 9 yeah, Vdd is shorted to ground by Q1,
but we are making use of this pn junction for a better bandgap reference.
please refer to Razavi Fig 11.14 for more details on how this circuit work
knows |
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m*******9
发帖数: 13 | 10 完全用pmos代替bjt毫无意义，你提到的Q1的接法也是错误的，s&d连起来都有2个p注入
的端点了，与nwell的关系就不再是单一的pn结了，用s&d中的一端与nwell形成pn结看
似合理些
不过我挺奇怪的，正常使用的cmos工艺中，bjt通常都是寄生三极管，如附件所示的黄
色部分。应该cmos工艺都有，你可以再咨询下代工厂。如果实在不行，也可以单独用结
成pn结的方法，Q1的地方用1个pn结，Q2就在与电流镜相接的地方到Q1结一个pn结 |
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w7
发帖数: 76 | 11 If you substitute pmos for bjt, that won't make a bandgap reference. Or you'
re doing sth. else with the ckt? |
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x****g
发帖数: 2000 | 12 s&d离得很远(相对于base厚度来说），可以认为是两个并列的diode,应该没什么影响的
好像我真的没办法连接Q2， |
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f*****0
发帖数: 489 | 13 like anything in life, you try to figure out why it works, how you want it
to work and when it doesn't work.
bandgap is just a fancy way of saying the Vbe differentially between two
differently biased be junctions. |
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m*******9
发帖数: 13 | 14 Q2就用nwell与p注入咯，你只是为了接成一个p-n junction的样子 |
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s******e
发帖数: 2181 | 15 that's good. thank you so much!
you can send the schematics to my mail box: w******[email protected] |
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s******e
发帖数: 2181 | 16 that's good. thank you so much!
you can send the schematics to my mail box: w******[email protected] |
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s******e
发帖数: 2181 | 17 that's good. thank you so much!
you can send the schematics to my mail box: w******[email protected] |
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f*****0
发帖数: 489 | 18
definitely. But textbooks are too expensive so I usually read datasheet
instead.
bandgap comes in many shapes and forms but lm113 is probably some of the
best examples on how bandgap voltage reference work.
so here it is.
can your bandgap textbooks tell us how it works? specifically, Q1/Q2/Q4 and
Q7/Q9?
it may help if you simplifies the schematic a little bit but I will leave
that to you. |
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f*****0
发帖数: 489 | 19 the attached schematic may help explain how the "simple diode" bandgap works.
it is essentially an unbalanced "current mirror". I1 > I2, and Vbeq1 > Vbeq2
. so the output voltage on R3, which is the Vbe differential between Q1 and
Q2, has a much lower but positive tempco.
this is what Bob Peace referred to as the "brutal force" bandgap.
you can run the bandgap much better if you input it with constant current
over the rail, by connecting the rail to a power source with a CCS or simply
with a res |
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f*****0
发帖数: 489 | 20
output
hooked
the pease article is for simplified schematic. yes, your design would work
but having a resistor (R9) there lowered the gain of the super linear pair (
Q7/Q9) (thus improves the stability) and also limits the amount of current
that can go through Q9.
correct on both accounts. |
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p***e
发帖数: 118 | 21 请问一下
刚毕业
想把学校里自己做过的PROJECT带走
如果想可以重RUN SIMULATION,
看到SCHEMATIC 跟SYMBOL
有哪些库需要COPY的???
Thanks |
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G******y
发帖数: 86 | 22 有什么好用的画电路软件，可以输出eps格式的文件的？这样latex里看起来就清楚多了
我现在是用visio画图，save as jpeg，然后用jpeg2eps转，效果不太好，大家都有什
么好办法？谢谢！ |
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Z*****i
发帖数: 1888 | 23 maybe you can try OpenOffice |
|
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f*****0
发帖数: 489 | 25 you can just print a document to a postscript printer and direct the output
to a file. many Apple / HP printers have postscript drivers. |
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w****a
发帖数: 11 | 26 visio可以直接选择存成eps，然后用ghost 转成pdf,如果需要的话。 |
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w********o
发帖数: 10088 | 27 能弄成eps以后首选illustrator啊,呵呵 |
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r****e
发帖数: 122 | 29 Virtuso是画layout的, composer才是画schematic. 你是这里笔误还是操作错误?
不知道这是不是跟你那error报告有关联.
行仿
下错
abso |
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b**s
发帖数: 231 | 30 做analog的，看书只是知道大概，想自己在家里学点感兴趣的。model file可以从一些
学校的课程里下到，我想知道哪里能下到free的软件，画schematic、产生netlist，和
做simulation。 |
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g****2
发帖数: 9 | 31 I had a PCB layout (.max) generated by old OrCAD program. Now I imported
this .max layout and opeded it in Cadenece PCB Editor. I want to create
gerber files based on this layout and some changes to the circuit.
My question is can I just do it in PCB Editor without touching the schematic
using Design Entry CIS?
More specifically:
1. How can I delete a connection line and add a new one between another two
components/nodes in PCB Editor?
2. How can I add a new component, say resistor, in the layou |
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f********o
发帖数: 2181 | 32 DC出来的schematic和cadence virtuoso不兼容啊
除非用OA格式的, 但是要库支持 |
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n***d
发帖数: 647 | 34 读硕士的时候我发明了一个东西，设计，测量了第一个版本，发了Journal。
接着我把电路设计大大改良了，把第一个版本和这个改良的电路同时申请了patent。
由于时间有限，改良版没有流片和测量。于是我就离开学校参加工作了。
之后来了个中国小弟，初来乍到接手我剩下的工作：画版图和测量这个改良版。其中我
跟他解答了不少问题。
经过一两年的折腾，现在测量结果令人满意，他要发paper了。
他跟我说我将会是第二作者。
我郁闷了：
这个电路从Idea到Schematic和Simulation都是我的，他的工作是Layout，Test和write
paper。
就像在公司，我是Engineer，他是Technician。
请问我该不该是第一作者？还有怎样跟他说这个事情？
大家给点意见吧。 |
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d****o
发帖数: 1112 | 35 这本不行吧
现在业界流行的是OrCAD or conceptHDL做schematics, Allegro做PCB,hyperlynx做sim
ulation
用orcad layout的是少而又少
PowerPCB也比这个流行吧 |
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h********t
发帖数: 555 | 36 if you want to focus on system level or board level design, many such kind
of systems are already on the market for many years.As a beginner, you want
to beat them? well, only if you are a genius.
if you want to focus on IC level design, take a look at the following
schematic, then ask your advisor which block he believes he could do better
at LOWER COST?
http://www.analog.com/library/analogDialogue/archives/29-3/low_power.html
recently, Freescale and Monebo take one step further. They are joint |
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g******u
发帖数: 3060 | 37 I agree.
Analog design is not something has a detailed standard, everyone has his
preference. maybe the software can propose a certain schematic, but the guy
just say: well, I don't give a crap. |
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R****a
发帖数: 199 | 38 What happens if you inject current to all three contacts?
Also, you made the laser or you buy/get it from somewhere else?
A schematic drawing of your laser might also be helpful (including the
waveguide structure and material).
1574nm)
this
bigger |
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s*******y
发帖数: 44 | 39 谢谢回复，我检查了RTL schematics，那个信号确实没有任何连接，而我的代码里是有
的，不知道为什么综合有问题。
level |
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c******s
发帖数: 197 | 40 orcad只是schematic，或许你说的是layout plus，好像现在layout都不卖了，cadence
只推allegro，据说是最牛x 的PCB 软件之一，我们这里都设计低速的电路，所以没有
特别的要求 |
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d****o
发帖数: 1112 | 41 orcad是最简单好用的schematics tool，cadence买它就是为了灭了它
搞得现在一堆bug丫也不修，全力推他的concept
allegro是最牛的PCB软件了，不过现在布线这种力气活都外包了吧
cadence |
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g******u
发帖数: 3060 | 42 No, I've been working for a few years in a small company.
we only have less than 5 electrical engineers, all old and very good, except
for me.
Thus I design schematics, draw layout, write codes, troubleshooting, deal
with manufacturing, everything. It's just no one will help me.
Although, it's lucky that we have a old lady who solder prototypes for us. |
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j****9
发帖数: 2295 | 43 今接了个电话，说要repairing circuit boards without the need of schematic. 需
要了解JTAG, VxWorks的人.
不是很懂。
有人了解么？ |
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h**g
发帖数: 94 | 44 schematic & layout: cadence virtuoso
simulation: cadence/spectre or synopsis/hspice
extraction: cadence/assura or mentor/calibre |
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g******u
发帖数: 3060 | 45 软硬通吃是可以，但是一个人能做的事情是有限的。我有时也一个人设计schematic,挑
元件，画layout,写程序，troubleshoot...但是，毕竟没法做很庞大复杂的系统。无论
硬件或者软件，钻进去水都太深。
所以有时还是羡慕大公司一个项目有十几个人一起做的。比较节约时间。 |
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s**g
发帖数: 66 | 46 please clarify your question.
your schematic is confusing. |
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s**g
发帖数: 66 | 47 Be patient, my friend.
Let me rephrase your OP:
You are trying to apply AC analysis to a ckt under such a 'bias' point,
which is only obtained through transient sim (periodic).
Here are my questions:
1. what is your switching freq? what is AC freq?
2. can you show your feedback ckt in the schematic?
There are different ways to attack this issue:
PSS + PAC may apply only when you try to study AC at a much lower freq than
switching frequency. But as you use it, your switch2 turns on/off all the
ti |
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f*****0
发帖数: 489 | 48
it depends on the gain of the amp. if the output swings close to its
rail at input close to 4v, you will have the problem you mentioned.
also, the cap you used to filter the ac content on the dc input terminal
may have an impact on the a/c input terminal - all depends on how you
designed the circuitry and without a schematic, no one can help you
more. |
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f*****0
发帖数: 489 | 49
the original schematic didn't show on my brower (.png file) so I am
resaving it in .jpeg format. |
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a****y
发帖数: 255 | 50 Suggested schematic from Hall sensor' datasheet is used, so it is not the
way I use it. |
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