r*****l
发帖数: 24 | 1 1. Phone interview
The extra inverter? 16 extra inverter?
I don't know what's extra inverter
2. On-site interview
Write down verilog
clock is divided 5
Does everyone can solve these problems?
Thank you. |
r***e
发帖数: 486 | 2 第一题，从后面的16来看，可能问的是hex inverter?
【在 r*****l 的大作中提到】
: 1. Phone interview
: The extra inverter? 16 extra inverter?
: I don't know what's extra inverter
: 2. On-site interview
: Write down verilog
: clock is divided 5
: Does everyone can solve these problems?
: Thank you.
|
A***J
发帖数: 478 | 3 never heard about the first
for the second question.
The way I implement it is like below
============================
`timescale 1ns/100ps
`define clk_period 100
module clk51(clki, rst, clko);
input clki;
input rst;
output clko;
reg clko;
reg[2:0] cnt;
always #`clk_period clki=~clki
always @ (posedge clki) //count to 5
begin
if(!rst)
cnt=0;
else if (cnt==5)
cnt=0;
else
cnt=cnt+1;
end
always @ (posedge clki) // clko
begin
if(!rst)
clko=0;
else if (cnt<5)
clko= |
t********t
发帖数: 5415 | 4 第二题clko不是50%的吧？要是50%的话奇数分频就得考虑negedge上做动作，或者有没
有别的办法？ |
D*e
发帖数: 5 | |
d****o
发帖数: 1112 | 6 其实这个用状态机做最简单。
【在 A***J 的大作中提到】
: never heard about the first
: for the second question.
: The way I implement it is like below
: ============================
: `timescale 1ns/100ps
: `define clk_period 100
: module clk51(clki, rst, clko);
: input clki;
: input rst;
: output clko;
|
d****o
发帖数: 1112 | 7 状态机+pos/neg edge
【在 t********t 的大作中提到】
: 第二题clko不是50%的吧？要是50%的话奇数分频就得考虑negedge上做动作，或者有没
: 有别的办法？
|
T******T
发帖数: 3066 | 8 extra inverters ? what is the entire question 1 ? |
