m**e
发帖数: 150 | 1 怎么说呢?非一日之功的说.
VHDL是最简单的了.现在常用的硬件设计语言大概就VHDL和Verilog
两种,我个人觉得verilog更简明,更好学,但基本上都和计算机语言
例如C差不多,比较好上手.然后就是用Veilog_XL(CADENCE)或者VSS
(SYNOPSYS)进行逻辑模拟验证逻辑功能,之后还可以利用SYNOPSYS
的综合工具综合成网表,然后再自动布局布线成版图,这属于半定制
的设计.另外有了VHDL语言对电路的描述以后好象还可以用自动工具
生成FPGA,这个我没有做过,不知道.
要是自己从版图入手设计就很烦了,一个小电路画起来也是非常费劲
的,所以有些公司里有一帮人专门画一些小单元电路,进行建库,另
一帮人进行高层设计,然后自动用这些库来生成版图.
Cadence是一个很大的工具,学会用其中一种功能不难,要想面面俱到,
是需要时间的. | c****t
发帖数: 220 | 2 many tools between SYNOPSYS & Cadence have the same function.
The strong point of Synopsys is synthesis(Design Compiler...) or
front end, Cadence is good at backend(Place Route,simulator).
Now, cadence has bought Ambit, so Cadence's would provide
a full strong tools set---from system model to final layout,
& new methodolgy also has been born,which will include your
timing thinking from system model design beginning,which can
reduce items between desgin stages.
Maybe Synopsys will merge with Avan |
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