A***J
发帖数: 478 | 1 never heard about the first
for the second question.
The way I implement it is like below
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`timescale 1ns/100ps
`define clk_period 100
module clk51(clki, rst, clko);
input clki;
input rst;
output clko;
reg clko;
reg[2:0] cnt;
always #`clk_period clki=~clki
always @ (posedge clki) //count to 5
begin
if(!rst)
cnt=0;
else if (cnt==5)
cnt=0;
else
cnt=cnt+1;
end
always @ (posedge clki) // clko
begin
if(!rst)
clko=0;
else if (cnt<5)
clko= |
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