le
发帖数: 190 | |
ET
发帖数: 10701 | 2 1.重新设计这个clock
2.pll
【在 le 的大作中提到】
: thanks
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le
发帖数: 190 | 3 假设这个clock是given，做个pll太麻烦了吧。
【在 ET 的大作中提到】
: 1.重新设计这个clock
: 2.pll
|
ET
发帖数: 10701 | 4 想不出还能有其它办法。
觉得总要找个reference clock有这么个50% duty cycle的。
pll其实也没那么复杂。
【在 le 的大作中提到】
: 假设这个clock是given，做个pll太麻烦了吧。
|
c******h
发帖数: 454 | 5 divide clock by 2 and use a DLL to align the rising edge with falling edge
and then shift 90 degree. XOR the divided clock and shifed 90 degree clock,
you will get duty cycle correction.It is a typical DCC circuitry. |
le
发帖数: 190 | 6 I understand your topology. To make it simpler, you can use a 4-tap DLL.
Actually I've seen DDC using two differential pairs with a simple feedback.
You can find the circuit in Dally and Poulton's book, but I am not quite
sure about its operation and limitation.
,
【在 c******h 的大作中提到】
: divide clock by 2 and use a DLL to align the rising edge with falling edge
: and then shift 90 degree. XOR the divided clock and shifed 90 degree clock,
: you will get duty cycle correction.It is a typical DCC circuitry.
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