p**f
发帖数: 7 | 1 Let's say we have
f(x)=sin(x), and thus f"(x)=-sin(x)
and let's use Fourier as
F(k)=\int f(x) e^{-i*2*pi*k*x}dx
and thus DFT as
F(n/NT)=\sum_{j=0}^{j=N-1} f(jT)e^{-i*2*pi*n*j/N}, n=0,...N-1
As a result, we should have
F[f"(x)]=-k^2*F[f(x)]
But if I calculate F[f(x)] use FFT, and then calculate F[f"(x)] according to
F[f"(x)]=-k^2*F[f(x)]=-(n/2pi)^2*F(f(x)), n=0,...N-1, NT=2pi
I cannot recover F[f"(x)]=F[-sin(x)]
what is the problem? I am really confused now. Thanks in advance. |
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m***l
发帖数: 264 | 2 我需要在fortran里面调用MKL的fft函数，可是老是无法使用那个DFT的库，而且也无法
编译那个库。
我用的是Compaq fortran 6.6，除了安装MKL以外，在调用库函数之前还需要设置路径
或者别的吗？有经验的麻烦回复一下，谢谢！ |
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m***l
发帖数: 264 | 3 需要在Fortran里调用做Discrete Fourier Transform的函数，不知道谁有简单好用的
Fortran源代码可以共享啊？
谢谢！ |
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j**u
发帖数: 6059 | 4 看看numerical recipes，www.nr.com |
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O******e
发帖数: 734 | 6 Numerical Recipes if you need to understand the code but don't care
about performance, FFTW if you need speed but don't care about the code. |
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w****g
发帖数: 44 | 9 Any body here developed the program for first-principles calculations ?
Such as DFT, HF ?
How are those programming compared to MD ? any books/other materials to
start with ?
Thanks |
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l*w
发帖数: 646 | 10 What is DFT, HF and MD?
What kind of problems are you solving? |
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w****g
发帖数: 44 | 11 DFT- Density Functional Theory
HF - Hartree-fork
MD- Molecular Dynamics |
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w****g
发帖数: 44 | 12 which one is harder to program ?
Do you know any book or other materials discuss the programming for DFT and
HF ? I want to learn this technique. I know many books on MD programming. |
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J*******3
发帖数: 1651 | 15 I run Siesta which is One of DFT.
commands I used is like this:
siesta < h2o.usercell.fdf > h2o.10Ang.out &
tail -f h2o.10Ang.out
The command line could not show up.
If I use
siesta < h2o.usercell.fdf > h2o.10Ang.out
Everything perfect fine! |
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n*y
发帖数: 7 | 16 multiple opennings at broadcom, San Jose, Irivine, San Diego
IC frontend, backend, DVT, DFT, SW (embedded).
If you are interested in it, please email your resume to me
g*****[email protected] |
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j*****n
发帖数: 1545 | 17 en 我觉得就像FT领域的 什么 DTFT,与DFT的关系一样， |
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t********s
发帖数: 5 | 18 到多少时都能，只要给的SAMPLE够多 。。。 |
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R******m
发帖数: 44 | 19 SAMPLE is finite, say n=100;
how can I do that? |
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t********s
发帖数: 5 | 20
嗯 ，那么，太近了就分不开了 。。。
随便找本儿DSP的书看看吧 。。 要知道
SAMPLING。 。。。 |
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R******m
发帖数: 44 | 22 我使用这个来计算spectrum。
s = 20 * log10(abs(fft(y)/N/afs*2));
N是采样数，afs 是振幅。
是对的吧？
谢谢 |
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z*****n
发帖数: 7639 | 23 well, you first need to analyse your signals.
What is the frequency/time domain properties
of these two signals respectively? If they
(at least one of them) have some special pattern
in time domain, you may try correlation.
If they don't overlap in frequency domain,
try FFT/DFT. |
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m****c
发帖数: 12 | 24 thanks.
I mean I only learned a little on signal and linear system.I want to know
DFT, FFT and so on |
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l******7
发帖数: 311 | 25 在东北部一个很一般的学校读phd，老板要去别的学校了，不想跟着去。想在这边拿个
master然后找工作，虽然master老板不太重要，但是还是想跟一个好找工作的，自己也
可以帮忙做点事，给找工作增加点经验。目标对准五个，他们研究方向分别是:
A: Computer-Aided Design and Test, Design-for-Testability (DFT), Delay Fault
Testing, Test Resource Partitioning, Secure Design, IC Trust, and CAD, Test
and Defect Tolerance for Nanoscale Devices
B: optimization for large-scale systems, 很多项目是电力公司的
C：Embedded system and integrated circuit design automation, power analysis
and optimization of ICs and systems
D：Computer microarch |
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p*****x
发帖数: 17 | 26 行行能出状元.我本科学核物理.现在做数字设计.好上手,数学会二进制就行.高数和数
理方程都还给老师鸟~~~
analog design -> cuicirt design for analog IP like PLL, DLL, Serdes, pad
design
digital design -> verification, RTL, top-level integration (STA, DFT etc)
layout design -> various CAD tools, floorplan, CTS, P&R, LvS, DRC
DSP and communication-> firmware, RTL, algorithm |
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t****i
发帖数: 182 | 27 This requires PCB level experience, ATE digital pattern generation, debug,
and ATPG DFT pattern debug experience. Most of the functional tests will
probably be done by the verification team, but you might need to know some
HDL to modify the testbench and re-gen some patterns. |
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j****9
发帖数: 2295 | 28 【 以下文字转载自 JobHunting 讨论区 】
发信人: jack19 (jack), 信区: JobHunting
标 题: EE MASTER 找工作求推荐
发信站: BBS 未名空间站 (Sun Jan 4 18:59:01 2009)
MS in EE.
VLSI/FPGA/ASIC的design/DFT/Verification 及其相关领域.有research经验。
no salary/location/travel requirement, better can sponsor H1B.
各位知道OPENING的大哥大姐们能否给我REFER一下呢。
站内联系。 |
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a****l
发帖数: 8211 | 29 变换就是换中说法说东西.比如一组数,0,1,2,3...100, 你可以告诉人家每一个数,也可
以告诉人家"从0开始到100,间隔1"两种说法都能得到相同的结果,这就是无损.但是如果
第二个数是5,你的方法就会损失一个数据,那就是有损. |
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D*e
发帖数: 5 | 30 非牛人.
前端：
1. Architecture design, mainly thinking and high level simulation. I think
this is the most important and fun part once you have gone through several
passes of the whole ASIC design flow.
2. RTL coding and verification by simulation using testbench
3. Assertion based formal verification
4. Logic synthesis using cadence RTL compiler of SNPS DC. Key is to
understand and develop SDC constraint file.
5. Logic equivalency check using Verplex or formality
6. DFT using scan insertio |
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u*****y
发帖数: 21 | 38 是我盗用了你的名字，还是你盗用了我的名字?
我是焊接电路板的 |
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a******s
发帖数: 176 | 40 We have a few openings in our company. If you are interested and willing
to relocate to Utah, please feel free to email your resume to me, I can
forward it to our HR.
BTW,
Experience is required for all positions
Firmware Engineer
General Overview:
Work within a team providing test relating to new and ongoing ASIC
products.
Duties and Responsibilities:
Evaluation of ASICs and related circuits
Investigate and define required test methods
Assure that test methods, including required DFT are implem |
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T******T
发帖数: 3066 | 41 Start looking into VERA, SystemVerilog etc since most of the verification
position needs those language skills. Getting familiar with ATE Testing/DFT
is also helpful since many of the functional verification suites can get
converted into functional test patterns/vectors for production testing. |
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A***J
发帖数: 478 | 42 不知道如何称呼这位，大侠，神人，牛牛，有啥书本推荐吗？？ 谢谢~~~
DFT |
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T******T
发帖数: 3066 | 43 DFT -> Design for test, it really is not directly related to ASIC
Verification field, but is an integral part of ATE testing so it doesn't
hurt to get some early exposure into it.
As for books on the Verification field, I really can't recommend any.
All the verif specific languages I've used like Vera and SystemC was on
the job self training. I would recommend that you visit the web site
www.asic-world.com. This is maintained by a Senior Verification Engineer
in India, and he does quite a good j |
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T******T
发帖数: 3066 | 44 俺觉得可能会问：
1）ATE 的问题，DFT/functional pattern generation/debug. Boundary scan,
at speed testing techniques, PVT on the ATE and Shmoo plot.
2) Analog/Mix signal circuit validation methodology for embedded LDO,
PLL, DAC/ADC, Digital/Analog I/O cells (slew rate control, drive
strength control validation).
3) Power/Ground integrity and its effect on the device, noise and
voltage level under min/max load, low<->high switching supply.
4) I/O characteristics validation, such as VIH/VIL,VOL/VOH, IOL,IOH,
I/ |
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T******T
发帖数: 3066 | 45 如果是面比较back-end的位置，别忘了多准备一些synthesis和static timing
analysis 相关
的知识. Ex:
STA: setting up proper constraints, false path/multi-path identification,
clock tree synthesis flows, load balancing etc.
Synthesis: Basic Flow, Common synthesis errors, critical warnings to watch
out for etc.
DFT: At speed testing techniques, MBIST techniques, Logic-BIST vs Inserted
Scan, Common device level failure modes for flops vs Memory. |
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m*****t
发帖数: 3477 | 46 【 以下文字转载自 Working 讨论区 】
发信人: justin10 (justin10), 信区: Working
标 题: Job Opening
发信站: BBS 未名空间站 (Tue Aug 10 01:12:53 2010, 美东)
A major semiconductor company in Santa Clara
Reqire:
1) Knowledge of VLSI, DFT
2) Experienced on c/C++ and TCL (or PERL) (real work experience)
3) Experienced on data structure (such as STIL of C++) (real work experience)
4) Experirnced on Algorithms (real work experience)
5) At least BS + 7 years experience or MS + 3 years experience or PhD + 2
year experience
6) Degree |
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s*****y
发帖数: 1974 | 47 差不多
不过还有布局布线，timing, DFT, layout，FPGA测试和软件verification
还有驱动开发，还有设计优化，功耗优化
大部分工作量在测试验证
算法开发占小部分工作量，因为现在的算法其实挺成熟的 |
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c*******n
发帖数: 442 | 48 小弟最近正在申请北美Fall 2011 PHD，而且申请的是据说最难的申请RF IC Design方
向。
想如果收的都是AD就找一个最好的从了……
在国内读研期间靠打些数字后端的工攒够了申请费 ~1500RMB/月，所以想问一下如果到
米国读PHD，类似的小工作好找么？（我的数字后端工作一般就是流片前一两周累死累
活，平时没事，我想这样的零工比较适合PHD做）
我的经验是~10万门级混合信号SoC数字后端(MCU+AD+LDO+RAM+FLASH)，从综合直到
Tapeout都能做（除了DFT）~ |
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f*********r
发帖数: 674 | 49 Senior VLSI/Physical Design Engineer
Submit ResumeSilicon Valley
This position requires an understanding of RTL to GDS flows, CMOS device
operation and advanced layout rules.
Responsibilities:
* Ownership of design floor planning, synthesis, DFT, place and route,
clock and power distribution, static timing analysis, signal integrity
analysis, physical verification.
* Use circuit design skills to verify clock and power implementation.
* Contribute to developing physical design methodo |
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e***y
发帖数: 4307 | 50 DFT is a discrete sampling of DTFT |
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