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EE版 - 喜欢ASIC VERIFICATION ENGINEER这个方向
相关主题
Verilog vs VHDLJob opening: ASIC design verification engineer
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求建议 ASIC ENGINEER 的面试要准备什么寻答案;半导体 夕阳产业
相关话题的讨论汇总
话题: asic话题: engineer话题: testing话题: 方向
进入EE版参与讨论
1 (共1页)
A***J
发帖数: 478
1
非常喜欢这个方向,感觉很有趣,不过我也属于入门级的,只有书本上的知识
非常喜欢 MICHAEL L. BUSHNELL 的, ESSENTIALS OF ELECTRONIC TESTING 这本书,
爱不释手啊。
有牛牛在这方面可以给我提点建议吗?MS 是CE方向,觉得学的还可以,就可能C++上面
弱了点,VHDL, VERILOG 应该没有问题
s*****y
发帖数: 1974
2

CE是什么?

【在 A***J 的大作中提到】
: 非常喜欢这个方向,感觉很有趣,不过我也属于入门级的,只有书本上的知识
: 非常喜欢 MICHAEL L. BUSHNELL 的, ESSENTIALS OF ELECTRONIC TESTING 这本书,
: 爱不释手啊。
: 有牛牛在这方面可以给我提点建议吗?MS 是CE方向,觉得学的还可以,就可能C++上面
: 弱了点,VHDL, VERILOG 应该没有问题

A***J
发帖数: 478
3
COMPUTER ENGINEERING
d****o
发帖数: 1112
4
computer engineering?

【在 s*****y 的大作中提到】
: 累
: CE是什么?

T******T
发帖数: 3066
5
Start looking into VERA, SystemVerilog etc since most of the verification
position needs those language skills. Getting familiar with ATE Testing/DFT
is also helpful since many of the functional verification suites can get
converted into functional test patterns/vectors for production testing.
A***J
发帖数: 478
6
不知道如何称呼这位,大侠,神人,牛牛,有啥书本推荐吗?? 谢谢~~~

DFT

【在 T******T 的大作中提到】
: Start looking into VERA, SystemVerilog etc since most of the verification
: position needs those language skills. Getting familiar with ATE Testing/DFT
: is also helpful since many of the functional verification suites can get
: converted into functional test patterns/vectors for production testing.

T******T
发帖数: 3066
7
DFT -> Design for test, it really is not directly related to ASIC
Verification field, but is an integral part of ATE testing so it doesn't
hurt to get some early exposure into it.
As for books on the Verification field, I really can't recommend any.
All the verif specific languages I've used like Vera and SystemC was on
the job self training. I would recommend that you visit the web site
www.asic-world.com. This is maintained by a Senior Verification Engineer
in India, and he does quite a good j

【在 A***J 的大作中提到】
: 不知道如何称呼这位,大侠,神人,牛牛,有啥书本推荐吗?? 谢谢~~~
:
: DFT

f*****g
发帖数: 112
8
方法学方面:
Writing Testbenches: Functional Verification of HDL Models, Second Edition,
Verify工程师人手一本的经典。
Reuse Methodology Manual for System-on-a-Chip Designs:重用设计的思想,芯片
设计的方向。
语言学方面:
具体什么验证语言,取决于公司。
如果什么都不会,就选一个SystemVerilog
t********t
发帖数: 5415
9
学习了...我也是类似方向
1 (共1页)
进入EE版参与讨论
相关主题
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Job Opening: Verification Engineer II (转载)求建议 ASIC ENGINEER 的面试要准备什么
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恳求工作内推: Electrical and Computer Engineering方向systemverilog到底有什么用?
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话题: asic话题: engineer话题: testing话题: 方向