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发帖数: 3477 | 1 【 以下文字转载自 JobHunting 讨论区 】
发信人: TroubleT (大麻烦), 信区: JobHunting
标 题: Couple ASIC Openings ( San Jose)
发信站: BBS 未名空间站 (Wed Mar 23 18:53:40 2011, 美东)
Hello, these just opened up, please submit via company website here :
http://tbe.taleo.net/NA1/ats/careers/searchResults.jsp?org=ATHE
Sr. Digital IC Verification Engineer
Responsibilities:
This position requires working with our architecture, design, and
verification teams to develop simulation and verification environments that
prove correctness and measure performance of our algorithms and RTL.
Responsibilities include developing simulation environments used by our test
development team to exercise Matlab and Verilog models, as well as evaluate
third party tools and develop methodologies which enhance our ability to
produce high quality ASICs.
Qualifications:
M.S. or Ph.D. in Electrical Engineering or Computer Science or Computer
Engineering. Candidate should have at least 5+ years experience with various
verification flows is required, with a proven track record of delivering
successful ASICs. A strong background in software is a must, along with
familiarity with ASIC design flows. Knowledge of wireless communication (or
other communication protocols) and good grasp of DSP fundamentals is
desirable.
Digital Design Engineer
Responsibilities:
- Digital Design of a complex Wireless Media Access Controller.
- Interface with Software team, to understand design requirements and take
the features through the ASIC implementation.
- Interface with the Verification team to create testing scenarios, and
isolate and debug test cases.
- Lab debug of prototyping and silicon bring-up.
Qualifications:
BSEE Required. MSEE preferred
- 3+ Years of hands on digital design and RTL coding.
- Capability to start from a high level specification and take the design
through the ASIC implementation process.
- Cross-functional experience interacting with SW team, Verification team,
Physical design team etc.
- Experience in lab-debug of ASICs or prototyping systems is a plus.
-Proficient in the use of industry standard languages and flows for RTL
coding, synthesis, functional verification, timing analysis, and scripting.
-Familiar with pre-silicon and post-silicon validation of ASIC designs.
-Experience in 802.11 and 802.3 protocols is a plus
Sr. Digital Design Engineer
Responsibilities:
Design and support of SOC ASICs, including interconnects and interface
modules.
Performance analysis of existing and planned SOC architectures.
Collaboration with SOC design teams in multiple geographies, primarily from
a hardware perspective but also interfacing with software teams.
Qualifications:
BS, MS or PhD in Electrical Engineering or Computer Science (MS or PhD
preferred)
At least 5 years of digital design and debug experience, with a proven track
record in a full product cycle covering specification, design, validation
through to volume shipment.
Working knowledge of CPU architecture, memory subsystems, on-chip bus
topologies, and off-chip interfaces including PCI express, USB, ethernet,
DDR/SDRAM/Flash.
Proficient in the use of industry standard languages and flows for RTL
coding, synthesis, functional verification, timing analysis, and scripting.
Familiar with pre-silicon and post-silicon validation of ASIC designs.
Performance analysis experience is highly desirable, for example profiling
or use of SystemC.
Excellent communication skills. | D********d
发帖数: 17 | 2 Thank you for providing this information. Are you currently with Atheros? |
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