n*l
发帖数: 44 | 1 I'm making a 6-layer board and went through the DRC error report. There're
approximately 1000 error related to every single via I have on the board.
Can anyone who has experience with Allegro PCB software give me a hand?... I
spent the past several hours and couldn't find a fix for it.
The error is:
"Shape to Thru Via Spacing
Required spacing 8 MIL
Constraint set name DEFAULT
Etch subclass VD2"
I made the via myself in the PadStack.
Thanks a lot!! |
c*******l
发帖数: 4801 | 2 your vias are too dense???
re
I
【在 n*l 的大作中提到】
: I'm making a 6-layer board and went through the DRC error report. There're
: approximately 1000 error related to every single via I have on the board.
: Can anyone who has experience with Allegro PCB software give me a hand?... I
: spent the past several hours and couldn't find a fix for it.
: The error is:
: "Shape to Thru Via Spacing
: Required spacing 8 MIL
: Constraint set name DEFAULT
: Etch subclass VD2"
: I made the via myself in the PadStack.
|
c*********6
发帖数: 858 | 3 Is the VD2 the power layer?
You maybe need to check you flash shape in your via.
re
I
【在 n*l 的大作中提到】
: I'm making a 6-layer board and went through the DRC error report. There're
: approximately 1000 error related to every single via I have on the board.
: Can anyone who has experience with Allegro PCB software give me a hand?... I
: spent the past several hours and couldn't find a fix for it.
: The error is:
: "Shape to Thru Via Spacing
: Required spacing 8 MIL
: Constraint set name DEFAULT
: Etch subclass VD2"
: I made the via myself in the PadStack.
|
n*l
发帖数: 44 | 4 Yes VD2 is a power layer. I made VD2 a negative plane.
I'm not sure what is a flash shape?.. Just looked in the PadStack, didn't
find
flash shape option.
【在 c*********6 的大作中提到】
: Is the VD2 the power layer?
: You maybe need to check you flash shape in your via.
:
: re
: I
|
n*l
发帖数: 44 | 5 There are some vias in the board are in the middle of nowhere, that is there
aren't any components within 75 mil of their vicinity, and those vias still
give me via-to-shape spacing error.
En, I set the constraint in Setup -> Constraint -> Physical (lines/vias)
rule set : Set Values .. |
c*********6
发帖数: 858 | 6 Flash shape in pad will decide how to connect or isolate the via to internal
layers like GND or POWER.
Normally you gotta design the flash before designing the pad or via.
【在 n*l 的大作中提到】
: Yes VD2 is a power layer. I made VD2 a negative plane.
: I'm not sure what is a flash shape?.. Just looked in the PadStack, didn't
: find
: flash shape option.
|
