w****8
发帖数: 33 | 1 因为项目需要，
需要找一个contractor做Verification工作，
三个月。
需要
1. 用UVM bring up testbench from scratch,
2. write testcases
3. documentation
4. migrate UVM testbench
所以需要有多年工作经验，或者你很自信你对UVM很熟。
工作地点：CA, SAN JOSE, H公司。
有意者可以发简历到[email protected]/* */
我会把你的简历转给我的manager。
有效期可能比较短，
因为其实HR已经开始在通过中介找人了。
谢谢 |
|
w******p
发帖数: 2 | 2 自己当初定位是要有奖才能出去。我前几天收到了University of Vermont的Stat
Master的offer。今天收到了正式邮件，但让我3.29之前答复去不去。我觉得去这个学
校读硕士将来再申请名校的博士也不错，但想了解下在UVM硕士毕业后申请美国博士能
申请到什么层次的学校。大家有谁有信息吗？大概能申请到什么学校的PHD？难度如何
？该如何规划？
如果我从了UVM，为了能申请到更好学校的PHD，硕士两年该注意什么呢？
但目前我还无法回复他们，因为我还要等OSU、NCSU、Rutgers、Purdue、TAMU的结果。
。。
现在的情况就是，如果OSU等五所学校任何一所给了我offer，我必然去。但就是不知道
它们能不能在10天内出结果。我觉得即使是在10天给了AD的话，也不能保证能有奖学金
的消息。。而且这些学校都已经发了第一轮的offer了，我觉得我唯一能进的可能性就
是有别人拒掉，这样即使有机会，也要等到4.15前后了。。。
我该如何答复UVM呢？
另外，还有个选项，如果有了德州的南卫理工大学（SMU）phd的offer（这个很早就给
了口头AD，有可能转成offe |
|
发帖数: 1 | 3 招聘 Digital Verification
需要熟悉 UVM
熟悉Wifi更佳。
有意者站内联系 |
|
|
a*****a
发帖数: 19262 | 5 确实挺难决定的，UVM 的统计不提供Ph.D, 基本上所有的 master 毕业后都是直接找工
作的。要说三年前，工作情况还不错，但是今年毕业的，还没听说谁的工作已经定下来
的，都很着急。
如果楼主想读Ph.D,确实需要慎重考虑，否则时间机会成本太大。 |
|
l******h
发帖数: 2 | 6 Highly reputational company with very competitive compensation for all
positions.
Please send in your resume and position/positions you like to apply to my
email address below.
h*******[email protected]
All resumes will be deliver to hiring manager directly. Act fast!
Thanks!
Silicon Engineering Group
Sr. Physical Design Timing Engineer
Timing (STA) Manager
Senior Physical Design Engineer
CAD Manager - Front-End Design and Verification
Sr. CAD Engineer - Place & Route / Physical Design Engineer
Sr. CA... 阅读全帖 |
|
L***s
发帖数: 9258 | 7 发信人: Mang (忙 盲 茫), 信区: TsinghuaCent
标 题: 任教于美国一流大学的部分清华学子
发信站: 水木社区 (Tue Sep 10 11:30:55 2013), 站内
【致谢】感谢参与编写和提供信息的以下校友：
IhateBS strong
根据美国US News 2013年美国大学排名前100的顺序统计，缺漏错误之处难免，请大家
补充
分为Full Professor（正教授）、Associate Professor（副教授）和Assistant
Professor三类，
其中前两类一般具有终身教职，不含解放前的清华学子，也含有极少数非tenure track
教职
人员,和已离职的人员，只列出，不计入统计总数。
共有在职Tenure track系列教职的共492 人，其中90名正教授。副教授186人
另有部分著名实验室全职研究人员22人
----------------------------------------------------------------------------
1,哈佛大学 6
林希虹
Professor, 生物统计系... 阅读全帖 |
|
l******h
发帖数: 2 | 8 Highly reputational company with very competitive compensation for all
positions.
Please send in your resume and position/positions you like to apply to my
email address below.
h*******[email protected]
All resumes will be deliver to hiring manager directly. Act fast!
Thanks!
Silicon Engineering Group
Sr. Physical Design Timing Engineer
Timing (STA) Manager
Senior Physical Design Engineer
CAD Manager - Front-End Design and Verification
Sr. CAD Engineer - Place & Route / Physical Design Engineer
Sr. CA... 阅读全帖 |
|
z****1
发帖数: 3840 | 9 【 以下文字转载自 NCAA 讨论区 】
发信人: zf2011 (张飞), 信区: NCAA
标 题: 【NBA版NCAA博彩】22场比赛88个赌盘 赔率2.0
发信站: BBS 未名空间站 (Thu Mar 16 11:05:56 2017, 美东)
来NBA版下注 支持你的球队
比赛开始准点封盘
http://www.mitbbs.com/mitbbs_lotterylist.php?board=NBA
标题(点击标题查看购买情况) 类型 开启者 售出 状态 结果
1 12:15 PRIN +6.5 > ND 单选 zf2011 1 可购 [查看]
2 12:15 PRIN +6.5 < ND 单选 zf2011 0 可购 [查看]
3 12:15 PRIN + ND > 135.5 单选 zf2011 0 可购 [查看]
4 12:15 PRIN + ND < 135.5 单选 zf201... 阅读全帖 |
|
z****1
发帖数: 3840 | 10 来NBA版下注 支持你的球队
比赛开始准点封盘
http://www.mitbbs.com/mitbbs_lotterylist.php?board=NBA
标题(点击标题查看购买情况) 类型 开启者 售出 状态 结果
1 12:15 PRIN +6.5 > ND 单选 zf2011 1 可购 [查看]
2 12:15 PRIN +6.5 < ND 单选 zf2011 0 可购 [查看]
3 12:15 PRIN + ND > 135.5 单选 zf2011 0 可购 [查看]
4 12:15 PRIN + ND < 135.5 单选 zf2011 0 可购 [查看]
5 12:40 UNCW +8.5 > UVA 单选 zf2011 0 可购 [查看]
6 12:40 UNCW +8.5 < UVA 单选 zf20... 阅读全帖 |
|
|
y****z
发帖数: 92 | 12 UVM最近拿到了60 millions donation, 学校正在大兴土木建教学楼和学生宿舍。 去年
的Cancer Moonshot是在UVM开的，它的Cancer Center也有不错的基金资助。不知楼主
拿的是哪个core facility的位置，我知道他们的DNA facility的director最近刚转到
工业界去了。 |
|
d******6
发帖数: 121 | 13 As a Design/Verification Engineer, the successful candidate will be
responsible for logic design, micro-architecture and functional verification
of high performance Ethernet PHY controllers with modern verification
technology, such as UVM. Responsibility includes understanding functionality
of SoC designs requirements, micro-architecture, Verilog coding, debugging,
developing test plans and components of verification environment, running
regressions, debugging failures, measuring functional and ... 阅读全帖 |
|
C******3
发帖数: 1 | 14 Master’s and Ph.D. student positions are available in the Multifunctional
Composites Manufacturing Laboratory (MCML) in Mechanical Engineering Program
, The School of Engineering, The University of Vermont, US.
The position is immediately available and open until filled.
The main theme of the research is “Advanced Manufacturing Technology for
Smart and Lightweight Polymeric and Hybrid Materials”.
The research areas will include: Macromolecular Materials, Micro-/Nano-
Additive Manufacturing (3D ... 阅读全帖 |
|
a*****a
发帖数: 19262 | 15 UVM的？难道我们认识？哈哈！UVM跟我同学的，我几乎没有不认识的。 |
|
d******6
发帖数: 121 | 16 As a Design/Verification Engineer, the successful candidate will be
responsible for logic design, micro-architecture and functional verification
of high performance Ethernet PHY controllers with modern verification
technology, such as UVM. Responsibility includes understanding functionality
of SoC designs requirements, micro-architecture, Verilog coding, debugging,
developing test plans and components of verification environment, running
regressions, debugging failures, measuring functional and ... 阅读全帖 |
|
m********g
发帖数: 10469 | 17 这就是帮三德子老婆洗屁股的行为，那个学校花１０００万买那块地换校就是自找死路
，BURLINGTON COLLEGE根本没那个偿还能力。旁边的UVM都不一定玩得起 |
|
b********n
发帖数: 38600 | 18 I'm suing the NBA. I suffered a devastating height disability at birth and
they won't accommodate my lack of upward vertical mobility (UVM) by allowing
me to play, unfettered, by an opposing team. |
|
|
|
f**********n
发帖数: 29853 | 21 我猜大部分是补充激素，直接下手把鸡鸡割了的应该很少吧。如果有那种直接下刀子的
医生真应该五马分尸。 |
|
|
G*******h
发帖数: 4091 | 23 补充激素也不应该，我觉得只能提供心理辅导。
：我猜大部分是补充激素，直接下手把鸡鸡割了的应该很少吧。如果有那种直接下刀子
的医生真应该五马分尸。 |
|
f**********n
发帖数: 29853 | 24 我也觉得激素也不应该。
以前有新闻说，想变男的女学生参加女性摔跤，天下无敌。她还说，俺还是客气的，激
素我只吃一半剂量了。 |
|
r*********t
发帖数: 4911 | 25 你们都没看到本质。这只是因为某些上层口味越来越重，正常的娃他们艹的兴致不如以
前高了。然而变性的娃又没处寻去（泰国的又太low), 于是得找医院立牌坊，显得很有
包容性。 |
|
n******e
发帖数: 1046 | 26 We could use a couple of verification engineers with extremely good perl
experience.
We have another with strong OVM/UVM experience
We have a few storage companies looking for strong design and verification
experience.
We have another for strong post silicon experience, cabling, power, etc.
We have a Sr manager opening for Hardware with experience in the home router
gateway space.
I appreciate your time and if we can help you at your current company please
let me know.
Mel
Principal
408-345-9100... 阅读全帖 |
|
l****y
发帖数: 5 | 27 working place is at Shanghai but with U.S. salary/compensation standard. The
candidate should speak Chinese/Mandarin. Some of the cases you only need
to stay in Shanghai for less than 6 months.
Interested party, please email resume to parkingsv(AT)yahoo.com
-----
Job description
The candidate will be responsible for the architecture and ASIC design and
co-verification of various 802.11 wireless baseband IPs within current and
next generation wireless products. The candidate will work within the ... 阅读全帖 |
|
m****s
发帖数: 18160 | 28 【 以下文字转载自 Returnee 讨论区 】
发信人: laoaky (laoaky), 信区: Returnee
标 题: 高通内推QUALCOMM 上海 Principal 200KUSD+
发信站: BBS 未名空间站 (Mon Mar 3 03:58:57 2014, 美东)
working place is at Shanghai but with U.S. salary/compensation standard. The
candidate should speak Chinese/Mandarin. Some of the cases you only need
to stay in Shanghai for less than 6 months.
Interested party, please email resume to parkingsv(AT)yahoo.com
-----
Job description
The candidate will be responsible for the architecture and ASIC design an... 阅读全帖 |
|
D******w
发帖数: 14 | 29 小弟去年五月EEMS毕业后去到上一家公司，今年四月正好在准备提交H1B申请的时候整
个组被裁掉了，之后几个月也断断续续有一些面试，但是机会比起去年少了很多感觉。
真诚求内推，方向是ASIC design/verification, 在原来公司做过RTL design，logic
synthesis，FPGA和UVM， 什么都碰过一点。
人在湾区，也不介意relocate到其他地方，如果有机会请大家多多关照，先谢谢了。 |
|
发帖数: 1 | 30 文思海辉 Pactera Technologies(www.pactera.com/en)热招 Pre-Silicon Validation
Engineer
接受OPT, H1b transfer
客户(项目): Intel
工作地点：Hillsboro, Oregon
Title: Pre-Silicon Validation Engineer
.
学历要求：BS or MS in Electrical Engineering, Computer Engineering or
Electrical and Computer Engineering
需要以下经验：
• Basic analog, mixed signal circuits
• Digital logic design and simulation using Verilog/VHDL
• 熟悉OVM/UVM or Verilog/VHDL
• high speed I/Os like DDR, PCI-express, USB or simila... 阅读全帖 |
|
l*****i
发帖数: 296 | 31 Novumind位处湾区，致力于人工智能应用的普及，去年年底获$16M A轮融资。目前
hardware team由前Intel Senior Director带队，AI加速器原型目前可以运行在FPGA上
并提供远超GPU的能效比，目前正在积极发展下一代硬件（demo请见 https://youtu.be
/TGQGStPoNu4）。我们正在积极寻找有VLSI背景的志同道合的朋友加入我们。
我们能提供具有竞争力的薪酬和福利，支持h1b和绿卡。
以下是JD：
Digital Frontend Engineer
You will be responsible for:
- microarchitecture design for cutting-edge AI accelerator
- system performance modeling
- RTL design and/or verification
Required Qualification:
- MS/PhD in EE, 1-2 year experience in digital design is a plus
- Ex... 阅读全帖 |
|
c**i
发帖数: 6973 | 32 Landing a postion is not necessarily good. As Taoism says.
Newest first.
(1) A friend of mine, an American male with some Puerto Rican background*
completed postdoctoral training (in 2-3 years?) at MIT with a no-name full
professor,** and was awarded assistant professorship at University of
Vermonet (UVM). I visited there and stayed for a month. Wow, his research
lab was an empty room, with an enpty incubator which immediately infected
mamalian cell cuture. The department gave him a small seed g... 阅读全帖 |
|
|
h*******3
发帖数: 42 | 34 如果你对这个职位感兴趣，请跟我联系。
地点在 San Jose, CA
Senior Verification Engineer
Job responsibilities:
Develop verification c-model for video codec and video processing
Develop verification environment and testbench components
Develop comprehensive test plans, design direct and random test cases
Perform RTL integration with firmware and help firmware debugging
Drive and adopt new verification methodologies and flows for efficiency
improvement
Assist with performance analysis and/or architecture
Desi... 阅读全帖 |
|
h*******3
发帖数: 42 | 35 【 以下文字转载自 EE 讨论区 】
发信人: huluwa123 (葫芦娃), 信区: EE
标 题: Open position
发信站: BBS 未名空间站 (Mon Apr 2 19:31:04 2012, 美东)
The position is in San Jose, CA.
Senior Verification Engineer
Job responsibilities:
Develop verification c-model for video codec and video processing
Develop verification environment and testbench components
Develop comprehensive test plans, design direct and random test cases
Perform RTL integration with firmware and help firmware debugging
Drive and adopt new verification... 阅读全帖 |
|
h*******3
发帖数: 42 | 36 下面这个职位贴了很久了，应者寥寥啊。有兴趣的话，给我站内信吧。
希望是有经验的。
This position is in San Jose, CA.
Senior Verification Engineer
Job responsibilities:
Develop verification c-model for video codec and video processing
Develop verification environment and testbench components
Develop comprehensive test plans, design direct and random test cases
Perform RTL integration with firmware and help firmware debugging
Drive and adopt new verification methodologies and flows for efficiency
improvement
Assist with perfor... 阅读全帖 |
|
v***6
发帖数: 42 | 37 fresh grad, 除了5年的经验要求不满足, 懂DV的也不多吧, 好像学校里现在还不教DV
吧, 包括什么UVM/OVM/VMM |
|
m*d
发帖数: 6 | 38 My group is expanding in phone/tablet area, opening for couple of positions:
Engineer position:
Linux Driver developer, USB2/3 experience is plus. Familiar with android/OS/
kernel.
Hw/sw co design, FPGA emulation, debug
Consumer electronics System integration&debug, preferred phone/tablet
experience
RTL design, simulation, test bench of uvm/svm/ovm experience
FW experience
Manager position:
Program manager, at least 4years management experience.
Please drop me resume if have one or two match |
|
r******9
发帖数: 129 | 39 Requirements:
* MS/PHD degree in EE
* Verilog / System Verilog (OVM/UVM) / any scripting language
* 4+ years industry experience
* Mixed signal verification experience is a big plus
站内联系
Thanks |
|
m****0
发帖数: 64 | 40 DC附近真不多，但会UVM的话东部还是有一些。
会的不多，最近在学习呢不过，呵呵，东部这类工作多吗？没看到啊，觉得西部很多。 |
|
n******e
发帖数: 1046 | 41 We could use a couple of verification engineers with extremely good perl
experience.
We have another with strong OVM/UVM experience
We have a few storage companies looking for strong design and verification
experience.
We have another for strong post silicon experience, cabling, power, etc.
We have a Sr manager opening for Hardware with experience in the home router
gateway space.
I appreciate your time and if we can help you at your current company please
let me know.
Mel
Principal
408-345-9100... 阅读全帖 |
|
l****y
发帖数: 5 | 42 working place is at Shanghai but with U.S. salary/compensation standard. The
candidate should speak Chinese/Mandarin. Some of the cases you only need
to stay in Shanghai for less than 6 months.
Interested party, please email resume to parkingsv(AT)yahoo.com
-----
Job description
The candidate will be responsible for the architecture and ASIC design and
co-verification of various 802.11 wireless baseband IPs within current and
next generation wireless products. The candidate will work within the ... 阅读全帖 |
|
l****y
发帖数: 5 | 43 working place is at Shanghai but with U.S. salary/compensation standard. The
candidate should speak Chinese/Mandarin. Some of the cases you only need
to stay in Shanghai for less than 6 months.
Interested party, please email resume to parkingsv(AT)yahoo.com
-----
Job description
The candidate will be responsible for the architecture and ASIC design and
co-verification of various 802.11 wireless baseband IPs within current and
next generation wireless products. The candidate will work within the ... 阅读全帖 |
|
D******w
发帖数: 14 | 44 小弟去年五月EEMS毕业后去到上一家公司，今年四月正好在准备提交H1B申请的时候整
个组被裁掉了，之后几个月也断断续续有一些面试，但是机会比起去年少了很多感觉。
真诚求内推，方向是ASIC design/verification, 在原来公司做过RTL design，logic
synthesis，FPGA和UVM， 什么都碰过一点。
人在湾区，也不介意relocate到其他地方，如果有机会请大家多多关照，先谢谢了。 |
|
s******e
发帖数: 52 | 45 有意者请给我发消息
Digital/Mixed Signal Design Engineer
Seeking a highly motivated and innovative digital/mixed signal design
engineer with strong theoretical and practical background in digital
circuits and FPGA design. Candidate with be part of a team responsible for
development of next generation AC/DC power management product and emulation
systems.
PRIMARY RESPONSIBILITIES
• Design and RTL coding of power management controller on FPGAs
from concept to production.
• Defining detailed... 阅读全帖 |
|
W******o
发帖数: 59 | 46 AMD has openings for cpu verification position。 These positions are mainly
for new college grads. Required skills including c++ programming, system
verilog, CPU architecture, experience with UVM, formal verificaiton, design/
verification tools is a plus.
如有兴趣请站内联系. |
|
m****s
发帖数: 18160 | 47 【 以下文字转载自 Returnee 讨论区 】
发信人: laoaky (laoaky), 信区: Returnee
标 题: 高通内推QUALCOMM 上海 Principal 200KUSD+
发信站: BBS 未名空间站 (Mon Mar 3 03:58:57 2014, 美东)
working place is at Shanghai but with U.S. salary/compensation standard. The
candidate should speak Chinese/Mandarin. Some of the cases you only need
to stay in Shanghai for less than 6 months.
Interested party, please email resume to parkingsv(AT)yahoo.com
-----
Job description
The candidate will be responsible for the architecture and ASIC design an... 阅读全帖 |
|
发帖数: 1 | 48 文思海辉 Pactera Technologies(www.pactera.com/en)热招 Pre-Silicon Validation
Engineer
接受OPT, H1b transfer
客户(项目): Intel
工作地点：Hillsboro, Oregon
Title: Pre-Silicon Validation Engineer
.
学历要求：BS or MS in Electrical Engineering, Computer Engineering or
Electrical and Computer Engineering
需要以下经验：
• Basic analog, mixed signal circuits
• Digital logic design and simulation using Verilog/VHDL
• 熟悉OVM/UVM or Verilog/VHDL
• high speed I/Os like DDR, PCI-express, USB or simila... 阅读全帖 |
|
l*****i
发帖数: 296 | 49 Novumind位处湾区，致力于人工智能应用的普及，去年年底获$16M A轮融资。目前
hardware team由前Intel Senior Director带队，AI加速器原型目前可以运行在FPGA上
并提供远超GPU的能效比，目前正在积极发展下一代硬件（demo请见 https://youtu.be
/TGQGStPoNu4）。我们正在积极寻找有VLSI背景的志同道合的朋友加入我们。
我们能提供具有竞争力的薪酬和福利，支持h1b和绿卡。
以下是JD：
Digital Frontend Engineer
You will be responsible for:
- microarchitecture design for cutting-edge AI accelerator
- system performance modeling
- RTL design and/or verification
Required Qualification:
- MS/PhD in EE, 1-2 year experience in digital design is a plus
- Ex... 阅读全帖 |
|
l****y
发帖数: 5 | 50 working place is at Shanghai but with U.S. salary/compensation standard. The
candidate should speak Chinese/Mandarin. Some of the cases you only need
to stay in Shanghai for less than 6 months.
Interested party, please email resume to parkingsv(AT)yahoo.com
-----
Job description
The candidate will be responsible for the architecture and ASIC design and
co-verification of various 802.11 wireless baseband IPs within current and
next generation wireless products. The candidate will work within the ... 阅读全帖 |
|
