l**t
发帖数: 10440 | 1 Senior ASIC Verification Engineer in Marvell Semiconductor:
Resposibilities include:
*Participate in early reviews of IP definition and architecture development
*Develop verification testplan for new design, build test bench, models,
test cases
*Interact with design team
*Perform rtl code coverage
Desired Skills & Experience:
*BS/MS degree in EE or CS with 5+ years of working experience in
Verification.
*Must have knowledge and experience of ASIC verification flows and
methodologies*Good Knowledge in languages relevant to the ASIC verification
process including Verilog,SystemVerilog, Unix Scripting, and C.
*Self-motivated, good communication skills and ability to excel in a team
environment.
*Experience in the serial bus such as PCIE/USB is a plus.
*Experience in gate level simulation/verification is a plus
Please send your resume to a******[email protected], thanks! | w***g
发帖数: 91 | 2 where does it locate?
development
【在 l**t 的大作中提到】
: Senior ASIC Verification Engineer in Marvell Semiconductor:
: Resposibilities include:
: *Participate in early reviews of IP definition and architecture development
: *Develop verification testplan for new design, build test bench, models,
: test cases
: *Interact with design team
: *Perform rtl code coverage
: Desired Skills & Experience:
: *BS/MS degree in EE or CS with 5+ years of working experience in
: Verification.
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