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发帖数: 3838 | 1 关于优化，有人说是我独家观点，实在太抬举了.
http://blogs.arm.com/software-enablement/377-risc-versus-cisc-w
In my first blog, we examined gave the historical context of the instruction
set battles of ARM and x86, covering the RISC-CISC Wars in the PrePC Era
and the PC Era. This blog covers Round 3, the PostPC Era [1].
Round 3: RISC vs. CISC in the PostPC Era
The importance of maintaining the sequential programming model combined with
the increasingly abundant number of transistors from Moore’s Law led, in
my view, to wretched excess in computer design. Measured by performance per
transistor or by performance per watt, the designs of the late 1990s and
early 2000s were some of the least efficient microprocessors ever built.
This lavishness was acceptable for PCs, where binary compatibility was
paramount and cost and battery life were less important, but performance was
delivered more by brute force than by elegance.
However, these excessive designs are not a good match to the smartphones and
tablets of the PostPC era. RISC dominates these “Personal Mobile Devices,
” because
It’s a new software stack and software distribution is via the “App Store
model” or the browser, which lessens the conventional obsession with binary
compatibility.
RISC designs are more energy efficient.
RISC designs are smaller and thus cheaper.
The table below from Microprocessor Report supports these last two claims[2]:
Comparing performance per megahertz, x86 is 4% - 8% faster than ARM or MIPS.
More significantly, this table suggests ARM and MIPS have 40% - 50% better
energy per MHz and their size is a factor of 3X to 4X smaller than x86.
Independent of these architectural battles, Personal Mobile Devices rely on
“Systems on a Chip” to reduce size, improve energy, and to lower costs. If
processors are available as IP blocks, any company can create a single SOC
rather than use many separate chips on a printed circuit board, as is the
case with PCs. Thus far, there is no serious x86 IP competitor to the many
fine RISC IP options, so SOCs based on x86 can only come from AMD or Intel.
RISC vs. CISC in the Client and in the Server of the PostPC Era
If Personal Mobile Devices are the clients of the PostPC Era, then Cloud
Computing is the server. Virtually all PostPC apps will have one foot in the
client and one in the cloud. While RISC has a substantial lead in PMDs,
CISC leads in the commodity server market that is the building block of
Cloud Computing.
Interestingly, binary compatibility again plays a small role in Cloud
Computing, and cost and energy efficiency again play a much larger role than
in PCs. Moreover, when you acquire 100,000 servers at a time to build a
Warehouse Scale Computer, custom microprocessors could make sense. RISC
competitors would need 64-bit addresses, ECC-protected memory, and good
virtual machine support to compete in the Cloud, but the door is not slammed
shut as it was in the PC Era.
Conclusion: RISC Reascendancy for Round 3
Note that the volume is on the side of PMDs in the PostPC Era: there will
surely be 100 chips built for PMDs for every chip made for Cloud Computing.
For 2010, even if you include the whole PC market—which you would expect to
fade eventually in the PostPC Era—the RISC chips still outnumber CISC
chips by 10:1 to 15:1.
Depending on your perspective, a happy result of the latest round of the
RISC-CISC Wars is RISC reascendancy.
_________________________________
[1] “Dawn of a New Day,” Ray Ozzie, http://ozzie.net/doc...n-of-a-new-day/, October 28, 2010.
[2] “Broadcom Shows Off New CPU,” Linley Gwennap, Microprocessor Report,
November 22, 2010.
David Patterson has been Professor of Computer Science at UC Berkeley since
1977. He is one of the pioneers of Reduced Instruction Set Computers,
Redundant Arrays of Inexpensive Disks, and Network of Workstations in
addition to being co-author of two widely-used textbooks on Computer
Architecture, now in their 4th editions. He is a member of the US National
Academy of Engineering, the US National Academy of Sciences, and the Silicon
Valley Engineering Hall of Fame. Recently, while exploring the perceived
value of Personal Mobile Devices in the PostPC Era, he made the shocking
discovery that iPads make excellent Christmas presents for your adult
children!
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David Patterson
06 May 2011 - 02:52 PM
While elegance isn't everything, its not nothing.
ARM may not be as elegant a RISC machine as some other RISC architectures,
but its a lot more elegant than the current x86. You're not going to find
factors of two between the various commercial RISC architectures, like we're
still seeing between x86 and RISC in the PostPC world.
When things are relatively close, then business models and other factors are
more important than architecture. ARM pioneered the use of the IP model for
supplying processors. This successful business model, which matches the
opportunities of Moore's Law along with needs of embedded computing market,
along with the technical advantages of RISC are the reason its so much more
popular in cell phones and tablets than x86. Its not merely a historical
accident, where technical and business issues have nothing say about to
explain the result.
0
MichaelK
07 May 2011 - 08:26 AM
sols, on 06 May 2011 - 05:54 AM, said:
...It is ironic that of all RISC ISAs ARM is actually the least elegant,
overloaded with unnecessary CISC-like features such as condition codes, pre/
post-increment addressing with shifting/scaling (even x86 addressing modes
are simpler).
Actually, as I'm programming now for 20 years in x86 assembler and ARM
assembler, I found that especially the features you mention (condition codes
, pre/post increment addressing with shifting) are features that are very
necessary and convenient for my purposes. Compared to that x86 is really
painful. I can't tell about other RISC implementations, but x86 compared to
ARM, programming the ARM in assembler is heaven like for me. It makes much
more sense in many ways.
I begin to "like" x86 assembler only when I learned to use SSE2, especially
for double precision, finally enough registers to use (still less than ARM
depending on 32/64bit on x86 and NEON version on ARM), but usable and the
feature of double precision and very very fast execution speed regarding the
desktop cores. It seems ARM's catching up with NEON, just at least me
missing the double precision feature...
0
sols
13 May 2011 - 06:01 AM
MichaelK, on 07 May 2011 - 09:26 AM, said:
Actually, as I'm programming now for 20 years in x86 assembler and ARM
assembler, ...
The goal of RISC was not to design an ISA for programmer-friendly assembler,
but to design an ISA that would be a good target for optimizing compiler.
Actually, CISC ISAs wanted to simplify assembly programmer’s life with
their complex orthogonal addressing modes.
Condition codes are bad for optimizing compilers because they cause extra
dependencies between instructions and restrict/complicate scheduling.
Also, when ARM developed Thumb extension they sacrificed these features for
code density, most likely, because they are not essential.
0
JackS
07 June 2011 - 12:11 PM
Hi Professor Patterson,I would like to seek your view on a few things:(1)
What's your view on the architecture of the datacenter today? Obviously now
are full of x86 servers which are run very inefficiently in the data
centers. Some of the CISC players have continued to increase the number of
sockets per server box and at the same time putting more cores on the same
die. What’s your view on the trends on number of cores and sockets in the
datacenter?(2) Totally agreed with your point that cloud computing is
going to be the server side in the post - PC era. How do you see ARM is
positioned to capture the public cloud? Which part of the cloud you think
ARM will be able to invade first ( I think it should be Linux based , Web
server ?) Correct me if I am wrong,(3) You mentioned Warehouse Scale
Computer, that’s the term Google used to build its datacenter; do you think
this is the efficient way to construct a datacenter? (Use low end commodity
single socket, multi core server and then scale out “or cluster” the
infrastructure with strong Ethernet) (4) Alternatively there are other
proponents in the market saying (i) Micro servers (Marvell , Intel’s
Atom ,AGCM, Calxeda) (ii) Some suggested packing a lot of low power CPU
like Atom or ARM cortex A9 in to one single server box sharing memory and
cache.(iii) Cisco Blade Servers. (iv) A private company Tilera is
trying to put as many core as possible in a single die and based on RISC as
well (non ARM) What do you see is the best solution, trends in socket /
cores in the datacenter? Please correct me if I am wrong and any view on the
datacenter would be greatly appreciated.Thanks a lot,JackS
0
David Patterson
08 June 2011 - 02:17 PM
JackS, on 07 June 2011 - 12:11 PM, said:
Hi Professor Patterson,I would like to seek your view on a few things:....
Lots of questions!
Regarding the questions on data centers/warehouse scale computing, the
upcoming 5th edition a book co-authored with John Hennessy (Computer
Archtiecture: A Quantitative Approach) dedicates one of the six chapters to
the subject. The chapter is 50 pages long, so I can't fit this all into a
blog entry. Here is an article about the next edition, which is coming out
in September:
http://www.ecnmag.co...me-Updated.aspx
Regarding ARM in a WSC, there are two concerns:
1) Computer architects think address space is important, so I think need an
ARM with a flat 64-bit address space to play a major role in the datacenter.
2) Urs Hölzle has mentioned the importance of latency in some critical
operations within a WSC, so there is an argument for a more sophisticated
microarchitecture in a WSC than is tradition in ARM. To see his arguments,
take a look at
Urs Hölzle, “Brawny cores still beat wimpy cores, most of the time,”
IEEE Micro, July/August 2010. | z*n
发帖数: 2893 | 2 首先应当表达对DP的尊敬, 这里学CS的很少没有拜读过他的那本计算机体系结构大作.
DP老先生有足够的资本可以提出个信仰问题, DP老先生一生推崇MIPS, 不幸的是x86风
光20年, 昔日的各种RISC实现一一夭折, 可说是生不逢时了.
不过信仰归信仰, 大家学科学的, 讨论技术问题, 重要的是数据和科学推理. DP老先生
从那简单图表所得的推论是不大符合科学精神的, 后面已经有人给了IBM Research的最
新文章劝老先生.
http://www.cs.sandia.gov/Conferences/SOS16/talks/Luitjen.pdf
实验数据给出的事实是:
Energy: ISA does not matter – system design does
– Packaging is the make or break dimension for exascale
No ARM ISA energy advantage measured – contradictory to rumors
– The u-server advantage lies in:
• Simple core leaves room to integrate ‘other stuff’ onto same chip
• Ethernet, USB, SATA, etc. integrated onto chip
• Significant energy savings by avoiding chip-crossings (System-on-a-
Chip)
用简单的话讲就是SoC是低能耗的原因, 不是ISA.
说句不敬的话, DP老先生思念RISC的辉煌时代有些痴了.
instruction
with
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【在 r******y 的大作中提到】
: 关于优化，有人说是我独家观点，实在太抬举了.
: http://blogs.arm.com/software-enablement/377-risc-versus-cisc-w
: In my first blog, we examined gave the historical context of the instruction
: set battles of ARM and x86, covering the RISC-CISC Wars in the PrePC Era
: and the PC Era. This blog covers Round 3, the PostPC Era [1].
: Round 3: RISC vs. CISC in the PostPC Era
: The importance of maintaining the sequential programming model combined with
: the increasingly abundant number of transistors from Moore’s Law led, in
: my view, to wretched excess in computer design. Measured by performance per
: transistor or by performance per watt, the designs of the late 1990s and
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