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发帖数: 121 | 1 As a Design/Verification Engineer, the successful candidate will be
responsible for logic design, micro-architecture and functional verification
of high performance Ethernet PHY controllers with modern verification
technology, such as UVM. Responsibility includes understanding functionality
of SoC designs requirements, micro-architecture, Verilog coding, debugging,
developing test plans and components of verification environment, running
regressions, debugging failures, measuring functional and code coverage and
improving test cases to meet coverage goals. The candidate also need to work
with backend designers to synthesize the Verilog code, close timing with PR
designers and help on all chip development process including chip debugging
with system engineers, ATE test patterns development with ATE designers.
要找senior level的，主要是做UVM verification。
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