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c***4
发帖数: 57 | 1 【 以下文字转载自 EE 讨论区 】
发信人: cxf54 (cxf54), 信区: EE
标 题: EE本科 CS master 电路设计 求内推
发信站: BBS 未名空间站 (Thu Apr 4 16:37:45 2013, 美东)
intel已经找到同学内推了
还投了broadcom和qualcomm的几个职位
求内推
主要经历
Power Gating QDI Stateless Systems
September 2010 – Present
Quantified reset timing assumption and proposed an algorithm to shorten the
wake-up latency of power-gated QDI systems
Simple Asynchronous Microprocess (SAM)
September 2011 – December 2011
Described SAM using Communicating Hardware Processes (CHP) and decomposed it
into logic gates
QDI SPI Master Controller
May 2012 – September 2012
Designed a QDI Serial Peripheral Interface (SPI) master controller for
serial data communication between a QDI AVR and a SPI FLASH memory
Designed Asynchronous Subthreshold Adders and FIFOs
July 2008 – June 2009
Designed a Frequency-Response-Masking Based Filter Bank
July 2009 – June 2010
Ultra-low power frequency-response-masking based filter bank for implantable
biomedical devices
Designed a 6-bit FLASH ADC
September 2007 – January 2008
Designed an Asynchronous 8051
September 2007 – May 2008
Designed an asynchronous 8051 using Balsa and synthesized layout using SOC_
Encounter.
谢谢了 |
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