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发帖数: 61 | 1 大家好，想就cache的MESI请教如下问题：
在如下RTL
I1: R1 <-[6]
I2: R2 <-[4]
I3: R3 <- R1 + R2
I4: [6]<- R3
I5: R4 <- R4 - 1
I6: [4]<- R4
Assume write-through cache policy. If memory block 4 and 6 are loaded onto
two different cache blocks (initially empty) on a single processor
我的答案是
Step/state Block 4 Block 6
Initial I I
I1 I E
I2 E E
I3 E E
I4 I E(write miss, AOW)
I5 I E
I6 E(write miss, AOW) I
请问正确吗？谢谢先。 |
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