m******1
发帖数: 25 | 1 刚提交了EB1A 140, 现在正准备485。我的情况是H1b到明年4月结束，这样的话，我该
如何准备employment verification letter. 是否可以让小秘不要写合同起止时间，而
只写title和salary. 或是直接到学校网站下载verification letter. 请好心人借鉴模
板。
还有，这种情况（非permenent job) 的RFE可能性有多大。谢谢！ |
|
s********e
发帖数: 133 | 2 如果公司不愿意出employment verification letter的话，请问EB1a提交485需要现公
司的offer letter来代替employment verification letter吗？需要的话是提供原件还
是复印件就行了？马上实行的J表对Eb1a提交485有什么影响吗？ |
|
j**a
发帖数: 71 | 3 其实我有三个问题。
第一个，我DIY的NIW 140批了, 可不可以停掉在给我办EB2(PERM还没完）?
第二个，为了省钱，想要现在的公司sponsor我的485。这个有没有什么问题？因为公司
的律师Fragomen可能没有办NIW485的经验。给律师有什么特别的嘱咐的。
第三个，NIW 485 需不需要Employment Verification Letter,因为NIW不需要employer
sponsor。如果要而且公司给我办485，这个Employment Verification Letter有什么
讲究？ |
|
K*V
发帖数: 192 | 4 大家都说交４８５的时候要公司出Employment Verification Letter，而且要元件，今
天问律师，律师回信＂The employment verification letter isn't necessary. We
can use your pay statements as proof of your continued employment.＂总感觉不
放心，有没有专家给解释一下，或者哪儿有官方的书面说明给个连接。谢谢！！！ |
|
b******p
发帖数: 11 | 5 现任雇主要我向前任雇主拿employment verification letter。而且必须是manager签
名。
可前任公司的移民顾问说他们只给由他签名的文件。就是说我拿不到manager签名的。。
现在两头一个说要紧一个说不要紧。。
我想问问，如果employment verification letter是由移民律师签名的，会不会被
audit?
有什么其他办法吗？如果前任公司不肯给manager签名的letter。
谢谢各位 |
|
L****y
发帖数: 72 | 6 我现在的公司办140时，已经把以前工作经历的employment verification letter费力
的弄好了，日期都快两年前的了，
现在看排期还是遥遥无期，又不让降级，只好准备跳槽，
问题是我能不能用带有以前日期的 employment verification letter 给我新的perm，
140用？
就担心时间隔得久了，不好再找人要证明信，而且跳槽让以前公司的经理不爽
同事都离开了，HR也换人了，就怕要新的letter不再好弄了，
大家都是怎么办的？
难不成就卡死在这里 |
|
a****a
发帖数: 13 | 7 先谢过各位大牛：
1. 我是学校律师办的。他要我问employment verification letter(EVL)，要有具体的
skill和duty的描述。可是我听说只是在填140的时候才需要EVL,为什么perm也需要？难
道我需要办两份，防止140的时候再需要？
2. 临毕业那学期，我在一个小公司做过四个多月的实习，本来他们希望我毕业后留下
来成为full time(实习刚开始就sign了future full time employment contract)，可
是我还是跳槽了。我担心他们不肯给我办employment verification letter. 万一真的
不肯，那么我的这些experience就会缺一小段，虽然别的经历加起来肯定能满足perm
requirement，可是会不会因为不连续而悲剧呢？
BTW：我的full time employment experience还差3个月才能满足perm requirement，
所以一定要实习的经历来补。我在这个小公司之前也有过较多的实习经历，所以加起来
就满足了。
10个包子酬谢！ |
|
发帖数: 1 | 8 As far as I know, you need R Letters to verify ur research. Also, u need
current job verification letter.
銆鍦navajogirl (navajogirl) 鐨勫ぇ浣滀腑鎻愬埌: 銆br />
璇種IW with advanced degrees, 闇鎻愪氦浠ュ墠 advisors, 鑰佹澘鎻愪緵鐨
Research Experience Verification Letters 鏉ヨ瘉鏄庢垜鎬诲叡鍋氫簡澶氬皯骞寸
殑 research 鍚楋紵璋㈣阿锛 |
|
m******e
发帖数: 82 | 9 我是国内master，国内有三年工作经验，在现任雇主之前在某西部小公司呆了半年，现
雇主要帮我申请绿卡，需要前雇主的Experience Verification Letter， 但是由于以
前和前雇主有过矛盾，他们不肯出具Experience Verification Letter。楼主应该怎么
做？ |
|
d**********g
发帖数: 1823 | 10 半年的经验，不写也罢。
[在 mknoodle (mknoodle) 的大作中提到：]
：我是国内master，国内有三年工作经验，在现任雇主之前在某西部小公司呆了半年，
现雇主要帮我申请绿卡，需要前雇主的Experience Verification Letter， 但是由于以
：前和前雇主有过矛盾，他们不肯出具Experience Verification Letter。楼主应该怎
么做？
：........... |
|
w*********s
发帖数: 277 | 11 4年functional verification经验。
主要是UVM/OVM，SystemVerilog，constrained random，functional coverage这些。
如果您的组或者你认识的组在招verification的职位，愿意refer的请pm，非常感谢！ |
|
m***e
发帖数: 48 | 12 【 以下文字转载自 JobHunting 讨论区 】
发信人: mafie (浪人~苦难中国), 信区: JobHunting
标 题: job openning: design verification in AMD
发信站: BBS 未名空间站 (Mon Aug 16 16:57:34 2010, 美东)
in case you are interested and qualified, please drop me a line.
Thanks
AMD's Graphics Memory Controller team is seeking an experienced RTL
Verification Engineer to impact areas such as dynamic power saving. The
candidate is expected to have a combination of hardware, software and debug
skills.
The detailed qualification is listed as below
- |
|
k*******y
发帖数: 79 | 13 【 以下文字转载自 EE 讨论区 】
发信人: kiddjacky (kidd), 信区: EE
标 题: ASIC verification job opening
发信站: BBS 未名空间站 (Sat Dec 4 23:24:14 2010, 美东)
我们组要招一个ASIC Verification Engineer. 要求MS,2-3年工作经验。我们组是做
SOC的。 如果有兴趣的话可以把RESUME发到k*******[email protected]。 谢谢! |
|
a****9
发帖数: 1983 | 14 转回自己家里，请德州的xdjm帮忙。
【 以下文字转载自 EB23 讨论区 】
发信人: ak1119 (阿卡1119), 信区: EB23
标 题: I140 employment verification letter
发信站: BBS 未名空间站 (Fri Mar 4 17:12:24 2011, 美东)
问个问题，申请140的时候，一定要把以前工作过的公司的employment
verification letter附上吗？
如果一定要附上，那么letter是不是必须由原来的公司出具才算数。今天问了一个以前
工作过的公司，居然叫我到 https://www.verifyjob.com/ 去拿。哪位有类似的经验吗
？谢谢
另外，140 premium processing有什么具体的条件？我的是eb2，master，2009年12月
开始的h1b，这些条件符合premium processing吗？谢谢各位大侠 |
|
d*******l
发帖数: 2567 | 15 Hi, folks, I receive these kind of emails from time to time. Since I have a
job, I guess
some of you might be more interested. So take it and good luck!
Please contact the recruiter directly but if you want ask me questions, feel
free and I'll try to help.
DB
Formalized Design Inc. is looking for Six (6) Sr. ASIC VHDL Verification
Engineers for a 15 months contract position in Dallas, TX.
The ideal candidate will have strong SoC ASIC Verification experience for DSP
processors & ASIC Co- Processo |
|
m****g
发帖数: 810 | 16 【 以下文字转载自 SanDiego 讨论区 】
发信人: maoing (SABRE), 信区: SanDiego
标 题: Graphics ASIC Verification opennings
发信站: BBS 未名空间站 (Wed Apr 14 02:43:22 2010, 美东)
Our group has several Verification opennings for Graphics (2D/3D) ASIC.
Prefer handson skills but may also consider excellent entry level candidates
. Will be exposed to Vera/System Verilog/VHDL/Verilog/OOP/RVM environment.
Required to be relocated to San Diego, CA if not local. |
|
c******s
发帖数: 338 | 17 You should check CA website to see if there is a FE verification form inside
the PE application. In general, it should have that form. Then, you should
fill that form and mail to New York state board with return postage to CA
state board. Also, you should contact with New York state board to make sure
the procedure and fee. Some states don't ask for fee such as Ohio but some
states request for couple dollars for the FE verification. Good luck. |
|
s***f
发帖数: 226 | 18 有点好奇，楼主不是很懂Verification的话是怎么能找到工作的，特别是现在这个情势
，很精通的人都不一定能找到工作。诚心请教。
做RTL Verification要很懂System Verilog，这个是很多职位的招聘基本条件之一。 |
|
m****g
发帖数: 810 | 19 【 以下文字转载自 SanDiego 讨论区 】
发信人: maoing (SABRE), 信区: SanDiego
标 题: Graphics ASIC Verification opennings
发信站: BBS 未名空间站 (Wed Apr 14 02:43:22 2010, 美东)
Our group has several Verification opennings for Graphics (2D/3D) ASIC.
Prefer handson skills but may also consider excellent entry level candidates
. Will be exposed to Vera/System Verilog/VHDL/Verilog/OOP/RVM environment.
Required to be relocated to San Diego, CA if not local. |
|
T******T
发帖数: 3066 | 20 Start looking into VERA, SystemVerilog etc since most of the verification
position needs those language skills. Getting familiar with ATE Testing/DFT
is also helpful since many of the functional verification suites can get
converted into functional test patterns/vectors for production testing. |
|
T******T
发帖数: 3066 | 21 Not sure for fresh grads, but these are fair game questions.
1) Verilog/VHDL, synthesizable coding style, common mistakes.
2) Design questions : clk div/N(odd), FSM, Async FIFO, Clock domain
crossing techniques, AMBA architecture, setup/hold timing related, maybe
some DSP questions.
3) Verification methodology, from design spec->requirements, testbench setup
, SystemVerilog/Vera/SystemC, assertion, code coverage, fsm coverage,
formal verif, lint, cdc, unit level sim vs system level sim. Random |
|
d******e
发帖数: 200 | 22 【 以下文字转载自 JobHunting 讨论区 】
发信人: deltisme (deltisme), 信区: JobHunting
标 题: Electrical/Analog verification 职位面试
发信站: BBS 未名空间站 (Thu Jul 8 20:58:03 2010, 美东)
请问electrical/analog verification 职位一般问点啥？
我是FRESH GRAD.有一些电磁，信号完整性的背景，VERILOG, VB不会，
对于FRESH的话，问点啥呢。 谢谢 |
|
l**********i
发帖数: 7 | 23 请发送简历到l************[email protected]
公司在徐汇区，标准美资企业，Fabless大公司，工作环境优秀，团队气氛友好，团结
向上,薪水也很不错，进来还发股票。
1. Verification Design Engineer--十暌陨暇椋比荒愎慌＃四暌陨弦部梢?-
要求高，当然薪水也高啦
Responsible for Design, Verification and customer support of protocol
systems. Good knowledge of High Speed Interconnects, Storage and
Networking Protocols, such as PCI Express, Ethernet, Fibre Channel, Serial
RIO, Interlaken. Good communication skill is must.
Experience with FPGA prototyping/validation a plus.
PREFERRED EXPERIENCE:
Design s |
|
N*****Z
发帖数: 70 | 24 最近正考虑转行，大家觉得CA和verification哪个出路好一些？个人比较喜欢CA，对
verification不是很了解。大家能不能给点建议,bow! |
|
h*******y
发帖数: 896 | 25 send me your resume if your background matches this position very well
========================================
Job Posting: Feb 15, 2011
Primary Location: US-TX-Austin-Oak Hill (TX30)
Job: IC Design
Education Level: Bachelor's Degree
Job Type: Experienced
Description:
Multimedia SOC Design Verification Engineer – Systems & Architecture
Engineer - Primary responsibilities are the definition, specification and
development of ARM based Multimedia SOC’s. Candidate must be able to work
with sales an... 阅读全帖 |
|
f******d
发帖数: 6361 | 26 he may not qualified for that, but as a phd , what he should do is design/r&
d, not verification/validation/testing, that is pretty much what a phd
program is designed for, unless his phd is focus on verification/validation/
testing. I won't be surprised if he feel shame of it.
for this kind of job you feel shame of |
|
P**********c
发帖数: 3417 | 27 Verification is just a different field than design. I don't feel either one
is inferior. Nowadays many verification problems are very challenging too.
势。 |
|
l**********y
发帖数: 68 | 28 想请教一下，verification上手是不是很难？另外，verification job前景和security
怎么样？实在是不太懂，请这里懂的人指导一下。先谢了。 |
|
h****p
发帖数: 175 | 29 verification 是cs的人做ee的事
cad 是ee的人做cs的事
cs = 累
ee = 钱少
越到下游进度越紧，因为前面的人耽误的时间老板希望通过压后面的人补上。
从上游到下游：
design-> verification -> 后端 (timing/physical) |
|
c*******c
发帖数: 726 | 30 很多做system verification prj的我个人觉得不比design容易，有些人好像背景更牛
比些，不过be基本都是被driven的，相对designer而言，验证师就比较不划算，技术含
量上verification貌似比validation还是要高级些的 |
|
O******2
发帖数: 210 | 31 刚收到santa clara Broadcom的Product engineer职位的offer。是1年的intern。暑假
fulltime，平时parttime。
但其实我是在申请ASIC/Mixed Signal IC verification/Design的intern职位，不过还
在等待消息.
现在的问题是broadcom要我3.29之前回复.
想问板上的同学：
1. 合同上面这样写的：
While interning at Broadcom, you will be subject to all of the company’s
policies and practices regarding employee conduct. Additionally, your
employment will be at-will, meaning that it can be terminated by either you
or the company at any time,with or without cause.
如果我拿到其他offer然后去做的话，会有什么后果。
2. ... 阅读全帖 |
|
S**********e
发帖数: 147 | 32 小弟现有两个offer,一个是通信公司的FPGA职位，主要做的是通信系统的研发，主要是
用FPGA去实现通信系统的一些DSP或interface的模块，会接触到通信的知识和比较多的
protocol的知识，也会做很多的testing。另一个offer是一家大半导体公司的CPU
Verification职位，VLSI/ASIC方向的应该对这类职位不会陌生，主要是用system
verilog,做verification。
小弟呢，一直对CPU方向很感兴趣，但考虑到摩尔定律快到头了，所以有点犹豫和踌躇
，不知道这类半导体公司十年后会不会走上裁员的道路，毕竟中年失业是很可怕的。可
是小弟也真的是很喜欢做CPU。。。以后如果国内有这方面的机会（国内毕竟还是落后
很多嘛），小弟还是希望能够回国。
至于FPGA，感觉受摩尔定律影响不那么大，毕竟很多地方都需要用到FPGA。但总感觉
FPGA做起来没有做IC那么升值快（如果我理解有偏颇，还望指正）。
所以小弟真诚希望版上的各位前辈，大神，能否帮小弟分析分析。小弟也不是没想过转
software,毕竟现在这个是趋势，也好赚钱，但小弟对做软件开发实在兴趣... 阅读全帖 |
|
y******8
发帖数: 48 | 33 论坛帐号太难注册，这是朋友的id，借来发个帖:
本人女，EE专业phd毕业，博士研究方向是Fpga加速图像处理算法，毕业后进了一家EDA
公司做码农，做design for verification。读书期间一直处于一心只读圣贤书状态，
毕业后才发现FPGA的就业面太窄，除了少数航空航天业会用到之外，就是一些小公司用
FPGA做些硬件接口，数据处理之类的非主流业务，工作机会少，职业前景差。我现在的
工作算是一个小换行，找到也纯属运气，以前一直写verilog，现在用C++做dev。当时
招我的主管说这行太难招到人，那是不是同时也可以理解为这行进来了想要跳槽也相当
难。但是现在半导体行业如此不景气，EDA也受很大影响。再加上行业内的恶性竞争太
厉害，感觉公司迟早走向并购裁员的那一天。我在linkedin查了查，发现进入EDA公司
的人要么一直待着不再挪窝，要么也只在EDA公司之间互相跳。
我想问下，EDA这行，尤其是verification方向将来前景如何（国内国外都说说）？关
于职业发展规划，应该朝什么方向发展？如果迟早都逃不了转行的命运，是不是不如趁
早彻底跳出来比较好？ |
|
t*******i
发帖数: 315 | 34 My status is also "Medical education credentials received and
verification is pending" and I called them. They said this means they haven'
t got the verification from our medical school. |
|
l*******6
发帖数: 34 | 35 The email from ECFMG says,
"This graduate status will be verified in one of three ways:
- ECFMG receives primary-source verification of the applicant's medical
education credentials; or
- The medical school verifies the applicant's graduate status through the
ECFMG Medical School Web Portal (EMSWP); or
- The medical school verifies the applicant's graduate status through the
applicant's Certification of Identification Form (Form 186)."
What does "primary-source verification" mean? Is it |
|
x****1
发帖数: 30 | 36 Do you think our medical schools should response the Form I-345 as well? If
so, there is no " titled verification of medical education" based on the
statement from Form I-345
" The Dean, or an authorized representative, of your medical school to
complete the attached form titled Verification of Medical Education". |
|
G**A
发帖数: 146 | 37 我的网上信息，终于显示出了 verification received date: July 27, 2009
这是不是说我的verification已经完成了？ 还是没有完，有进一步的动作？ |
|
y******9
发帖数: 1392 | 38 请问如何去学校找ECFMG发给学校的Diploma Verification letter, Letter的邮寄地址
上面会出现我的名字吗？还是去收发室只要看到ECFMG邮寄的信件都栏下来？
如果打电话要求ECFMG用FEDEX邮寄Verification letter的话，可以要求ECFMG按照我们
提供的地址邮寄么？因为应该邮寄到档案馆而不是学校校部得地址。
ECFMG邮寄出第一封信后多久才会给用FEDEX邮寄第二次？
谢谢解答！ |
|
j**h
发帖数: 185 | 39 马上要去一个面试, 昨天PC发了一个EMAIL, 要prepare some documents. 其中一条为:
* Written verification, with an evaluation of your performance, for any
clinical training obtained in United States Hospitals for which you received
educational credits.
估计这可能是给US 医学生准备的. 但自己也不想空手而去. 本人没做过externship, 只
做了OB. 申请时,OB的attendings 都给了LoR. 现在应该咋办呢? 请OB的医生再写个
verification letter or copy 原来的LoR 带去? 大家遇见过同样的经历吗? 或者可以
给些 ideas 吗?
谢谢先! |
|
e******e
发帖数: 364 | 40 我最近renewal我的CA letter（PTAL）， agent说让我注册提交FCVS。 我一查是FSMB
的CREDENTIALS VERIFICATION。
verification process问到了pre-med school的问题。 不知道怎么填，谁填过啊？CMG
怎么填这一项？
多谢。 |
|
l*****c
发帖数: 51 | 41 I received a letter from ECFMG saying " This is to notify you that ecfmg has
received direct verification of your final medical school diploma and your
final medical transcript from your medical school". Does this mean my 327
form has passed ecfmg verification? Thanks! |
|
l*****c
发帖数: 51 | 42 I received a letter from ECFMG saying " This is to notify you that ecfmg has
received direct verification of your final medical school diploma and your
final medical transcript from your medical school". Does this mean my 327
form has passed ecfmg verification? Thanks! |
|
s*****1
发帖数: 2312 | 43 刚发现信用卡被 FP 收了1分钱。这个账号我是取消auto top-up的。
是否需要去把这1分钱要回来？
Date Time Transaction # Description Paid
Product Description Qty Price Total
Account Verification Maintain Active Status 1 $0.01 $0.01
Shipping: $0.00
Taxes: $0.00
Deposit: $0.00
SubTotal: $0.01
Total: $0.01
Mar 29, 2017 11:03 PM 57059172 Account Verification $0.01
Mar 11, 2017 8:06 AM 55905968 Monthly Charge $0.00 |
|
s******g
发帖数: 3530 | 44 【 以下文字转载自 sysop 讨论区 】
发信人: sweetbug (正牌网站买买提首席侦探), 信区: sysop
标 题: 表扬老邢闻过即改，取消one more step verification
发信站: BBS 未名空间站 (Wed Jul 30 10:16:02 2014, 美东)
这种损人不利己、庸人自扰的愚蠢做法 |
|
s******g
发帖数: 3530 | 45 【 以下文字转载自 sysop 讨论区 】
发信人: sweetbug (正牌网站买买提首席侦探), 信区: sysop
标 题: 表扬老邢闻过即改，取消one more step verification
发信站: BBS 未名空间站 (Wed Jul 30 10:16:02 2014, 美东)
这种损人不利己、庸人自扰的愚蠢做法 |
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E*V
发帖数: 17544 | 46 http://news.yahoo.com/s/ap/us_obama_birth_certificate
Hawaii Health Director Dr. Chiyome Fukino issued statements last year and in
October 2008 saying that she's seen vital records that prove Obama is a
natural-born American citizen.
But the state still gets between 10 and 20 e-mails seeking verification of
Obama's birth each week, most of them from outside Hawaii, Kim said Tuesday.
If the measure passed, the state Office of Information Practices could
declare an individual a "vexatious requeste |
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g******l
发帖数: 31 | 47 我住在NJ，在NYC买了一辆加州title的车，注册out-of-state的车需要VIN
verification。网上搜搜，没搜到什么结果。只找到一个答案，NJ只有三个能对
rebuilt title进行检查的点。（而且这三个都很远）但我这不是rebuilt title。
求解！ |
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g********7
发帖数: 33 | 48 前一阵，我的车在停车场被一辆车给撞了，当时叫了警察，但是后来那个司机和我商量
（中间还有些小事情），就私了了，他赔了些钱给我。因为是第一次出这样的事，我还
是缺乏经验，以为不走保险公司，也就这么结束了。可是最近收到个BMV的notice，
Financial Responsibility verification。 It says"Indiana law requires that
you provide the BMV evidence of financial responsibility for the motor
vehicle involved." 像我和那个司机私了了，也没有什么evidence，应该怎么办呢？
谢谢！ |
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T*******u
发帖数: 55 | 49 新泽西州，买二手车时，报交易税时为付款的一半，现金交易。
三个月过去了，收到了一封蛮官方的Verification of Sales。说我报的价格低于市场
价，给我两种选择。一，补齐税款。二，找当时的卖方签署一份seller的说明，证明确
实是低价卖的。
现在的问题是，卖方不容易找。
如果我们要求补齐税款，年底报税时有没有其他罚款？会不会有不良记录？
多谢多谢！ |
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i******e
发帖数: 3 | 50 请问有没有这个dealer的"Dealer Verification Code", 收到个OFFER-试车给$75, 刚
买了车, 实在没时间去试肯定一时不会买的车. 谢谢 |
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