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全部话题 - 话题: multisite
1 (共1页)
b******s
发帖数: 1089
1
算了,我给了abstract吧:
multisite gateway为什么colony看起来很正常(spec resistant),PCR结果不稳定,
sequence结果悲剧?
j*********r
发帖数: 24733
2
来自主题: USANews版 - Seattle's $15 minimum wage costs jobs
New study of Seattle's $15 minimum wage says it costs jobs
SEATTLE – Seattle's $15-an-hour minimum wage law has cost the city jobs,
according to a study released Monday that contradicted another new study
published last week.
A University of Washington team studying the law's effects found that the
law has boosted pay in low-wage jobs since it took effect in 2015, but that
it also caused a 9 percent reduction in hours worked, The Seattle Times
reported . For an average low-wage Seattle worker, ... 阅读全帖
S*******h
发帖数: 7021
3
【 以下文字转载自 USANews 讨论区 】
发信人: jerrycasper (Cat), 信区: USANews
标 题: Seattle's $15 minimum wage costs jobs
发信站: BBS 未名空间站 (Tue Jun 27 17:10:11 2017, 美东)
New study of Seattle's $15 minimum wage says it costs jobs
SEATTLE – Seattle's $15-an-hour minimum wage law has cost the city jobs,
according to a study released Monday that contradicted another new study
published last week.
A University of Washington team studying the law's effects found that the
law has boosted pay in low-wage jobs since it too... 阅读全帖
c******n
发帖数: 16666
4
【 以下文字转载自 USANews 讨论区 】
发信人: jerrycasper (Cat), 信区: USANews
标 题: Seattle's $15 minimum wage costs jobs
发信站: BBS 未名空间站 (Tue Jun 27 17:10:11 2017, 美东)
New study of Seattle's $15 minimum wage says it costs jobs
SEATTLE – Seattle's $15-an-hour minimum wage law has cost the city jobs,
according to a study released Monday that contradicted another new study
published last week.
A University of Washington team studying the law's effects found that the
law has boosted pay in low-wage jobs since it too... 阅读全帖
l********g
发帖数: 68
5
来自主题: Classified版 - Xilinx openning
借用朋友的帐号发帖。
组里最近有openning.感兴趣的请站内回信。
Job Posting Title IRC97918
Job Title Senior Design Engineer
Detailed Description
Xilinx is looking for a highly qualified IC design engineer to join
the clocking hardware design team. This individual will work on digital
design of clock management blocks (eg, PLL, DLL) and clock distribution for
next generation FPGAs. The engineer will be involved in the entire design
process including RTL design, schematic gene... 阅读全帖
t******p
发帖数: 810
6
来自主题: ebiz版 - 这个在local邮局能买到吗?
https://store.usps.com/store/browse/productDetailSingleSku.jsp?categoryNav=
false&navAction=push&navCount=2&atg.multisite.remap=false&categoryId=flat-
rate-shipping&productId=P_LFRBPC1
G***y
发帖数: 1082
7
来自主题: Faculty版 - 史上最牛的论文ZT (转载)
lol, a replication study:
A Multisite Cross-Cultural Replication of Upper's (1974) Unsuccessful Self-
Treatment of Writer's Block
http://www.ncbi.nlm.nih.gov/pmc/articles/PMC2078566/pdf/jaba-40

138
l********g
发帖数: 68
8
来自主题: JobHunting版 - Xilinx openning
借用朋友的帐号发帖。
组里最近有openning.感兴趣的请站内回信。
Job Posting Title IRC97918
Job Title Senior Design Engineer
Detailed Description
Xilinx is looking for a highly qualified IC design engineer to join
the clocking hardware design team. This individual will work on digital
design of clock management blocks (eg, PLL, DLL) and clock distribution for
next generation FPGAs. The engineer will be involved in the entire design
process including RTL design, schematic gene... 阅读全帖
m****s
发帖数: 18160
9
来自主题: JobMarket版 - Xilinx openning
【 以下文字转载自 EE 讨论区 】
发信人: lordofring (闲云野鹤), 信区: EE
标 题: Xilinx openning
发信站: BBS 未名空间站 (Thu Aug 22 00:39:40 2013, 美东)
借用朋友的帐号发帖。
组里最近有openning.感兴趣的请站内回信。
Job Posting Title IRC97918
Job Title Senior Design Engineer
Detailed Description
Xilinx is looking for a highly qualified IC design engineer to join
the clocking hardware design team. This individual will work on digital
design of clock management blocks (eg, PLL, DLL) and clock distribution for
n... 阅读全帖
r********n
发帖数: 300
10
来自主题: Working版 - Hiring (转载)
【 以下文字转载自 SanFrancisco 讨论区 】
发信人: ricevision (孰能生巧), 信区: SanFrancisco
标 题: Hiring
发信站: BBS 未名空间站 (Wed Nov 10 01:12:44 2010, 美东)
(Several client side mobile app developers and server side Ruby developers and the following... drop your resume if interested)
Senior Operations Engineer
What you’ll be doing:
We are looking for a senior operations engineer to join our rapidly growing
team. You will be responsible for the security, stability, and scalability
of our production infrastructure. You’ll ge... 阅读全帖
r********n
发帖数: 300
11
来自主题: SanFrancisco版 - Hiring
(Several client side mobile app developers and server side Ruby developers and the following... drop your resume if interested)
Senior Operations Engineer
What you’ll be doing:
We are looking for a senior operations engineer to join our rapidly growing
team. You will be responsible for the security, stability, and scalability
of our production infrastructure. You’ll get to work hands on with plenty
of exciting scale challenges as we grow to support tens of millions of users
across hundreds of se... 阅读全帖
g***l
发帖数: 18555
12
一个搞熟了就有的是饭吃了,就怕两个都是半瓶子醋,你给人说两个都熟,没有人信的
,没有公司两家都用的,两个都用的可能是医院学校啥的,光SQL SERVER一个版本一个
版本的出,根本就跟不上,64BIT MULTISITES CLUSTERING加MIRRORING加REPLICATION,看着头都大,
明年再出2010,又要跟着忙活了。我觉得把一个搞熟,争取去微软镀镀金,考个MVP,我看好多
MVP都是老印啊,其实也不难的。

一倍
a*******s
发帖数: 1539
13
来自主题: Biology版 - paper help
Title:
Development of an optrode for intramural multisite optical recordings of
Vm in the heart.
Authors:
Byars JL, Smith WM, Ideker RE, Fast VG
Journal:
J Cardiovasc Electrophysiol (2003) 14:1196-1202
ID:
PN53810
my email is h*****[email protected]. thanks
m******e
发帖数: 18
14
来自主题: Biology版 - 问个克隆问题
MultiSite Gateway® Pro Plus (for flexible cloning of up to four DNA
fragments into a Gateway® Destination vector) from Invitrogen, you can
clone multiple DNA fragments into one vector without using restriction
enzymes or ligases.
w******d
发帖数: 46
15
There are some publications about that. I am just wondering if anybody have
some personal experience with this system. Is it easy to work with?
Thanks!
b******s
发帖数: 1089
16
我做三片段连接。entry clone都测过序。但是三片段重组之后总是有一些问题。首先
,每次都有colony。我用不同片段和载体上的primers检测,有时候有些primer组合出
带,有些不出。有时候带还不错,但是size有些移动。最后只好又去测序。有些克隆的
峰乱糟糟叠在一起。有些有clean的峰,但是sequence又不完全match。克隆重复划板,
liquid culture都非常正常。
我一般程序是三片段entry clone加载体每个大约1-1.5ul,LR clonase 1ul,25度反应
18-24h, heat shock之后培养2-3h再涂板。反应和培养时间是否太长?重组反应时间太
长会有问题吗?
另外,我所有的东西都是从同实验室日本博后那要来的。entry clone我自己后来测过
序,但是载体没有。原本来怀疑是载体,就用酶切检测没成功。日本博后告诉我载体是
改造过的,真实序列和他给我的sequence可能不一样。我用几对primers检测,都是对
的。
有经验的能否指教一下可能问题在哪?谢谢
s********n
发帖数: 2939
17
你得到的Clones的sequence是些什么东西?还有就是你的Destination vector的序列正
确吗?
i***l
发帖数: 1656
18
sequencing all constructs you start with
make sure stuffs are correct at the beginning
b******s
发帖数: 1089
19
来自主题: Biology版 - 再问gateway cloning
本来容易的gateway cloning成了最近几个月摧毁我身心健康的罪魁祸首。
哎,说来话长。先来介绍背景:1年前开始用gateway做克隆。在此之前实验室也一直用
gateway,但是实验室很小,我之前只有一个日本博后。做了好几年。几乎所有的东西
都是从他那里来。我们用的是multisite gateway,细说就是三个entry clone和载体一
起连。
我做了N次(我都不好意思说N等于多少了),一个确定的都没成功。
症状:每次连接之后转e coli都有菌落,而且菌落看起来正常。介入液体摇也正常生长
(spectinomycin resistance)。但是colony PCR有时会有不浓的bands,size貌似正
确,但是很多时候PCR失败。提plasmid PCR也失败,酶切也失败。
可能一:entry clone有问题。用gateway做entry clone很容易,应该不会,我做了好
几个entry clone,都sequence过,PCR检测等很正常。
可能二:我哪里做错了。至少我现在想起来应该没有。我经过无数次改进,从反应DNA
浓度到反应时间到heat shoc... 阅读全帖
b******s
发帖数: 1089
20
如果只是单个entry vector到destination vector,效率很高。
我做过大于6KB的都没问题。
但是我做multisite 3-way recombination效率极其低,还有很多false positive。
w******d
发帖数: 46
21
Anybody used this cloning kit from Invitrogen? I am trying to persuade my
boss to get the 3-fragment one, but it's not cheap (>$2000) and my boss is a
cheap one.
If you used it, what you like it? Doesn it worth the money?
Thanks!
l********a
发帖数: 61
22
想同时做三个相隔很远的点突变,大家能给推荐个好用的kit吗?自己查了下,有
Agilent Technologies的QuikChange Lightning Multi Site-Directed Mutagenesis
Kit,还有Life Technologies的GeneArt® Site-Directed Mutagenesis PLUS Kit
,原理看上去还不太一样,不知道哪个好用一点
s******r
发帖数: 1245
23
别折腾了直接合成吧
IDT的gblock片段1kb才一百多块,弄几个片段回来自己拼一下就好了
自己做突变买kit引物成本也不小还费时间最后没经验的还不一定做的出来

Kit
w******n
发帖数: 767
24
一只Dpn I足以。

Kit
l********a
发帖数: 61
25
什么意思,就用普通的kit做?
j****x
发帖数: 1704
26
QuikChange方法不需要单独买kit,引物用它家网站上的提供的server来设计然后自己
去合成,PCR polymerase用Phusion或者Q5,再订一只DpnI,就齐活了。这个方法简单
明了,成功率很高,用不用kit都一样。
l********g
发帖数: 68
27
来自主题: EE版 - Xilinx openning
借用朋友的帐号发帖。
组里最近有openning.感兴趣的请站内回信。
Job Posting Title IRC97918
Job Title Senior Design Engineer
Detailed Description
Xilinx is looking for a highly qualified IC design engineer to join
the clocking hardware design team. This individual will work on digital
design of clock management blocks (eg, PLL, DLL) and clock distribution for
next generation FPGAs. The engineer will be involved in the entire design
process including RTL design, schematic gene... 阅读全帖
1 (共1页)