c********0
发帖数: 104 | 1 Please send your resume to c*********[email protected] if you are interested.
This is a permanent job opening in Marvell.
Requirements:
1) Familiar with IC design digital flow, familiar with DC and PT
2) Experiences on design verification with SystemVerilog and UVM
3) Experiences with SVA
4) BSEE or MSEE
5) 3+ year experiences with Verilog
Thank you |
c********0
发帖数: 104 | 2 No one interested?
【在 c********0 的大作中提到】
: Please send your resume to c*********[email protected] if you are interested.
: This is a permanent job opening in Marvell.
: Requirements:
: 1) Familiar with IC design digital flow, familiar with DC and PT
: 2) Experiences on design verification with SystemVerilog and UVM
: 3) Experiences with SVA
: 4) BSEE or MSEE
: 5) 3+ year experiences with Verilog
: Thank you
|
b**********5
发帖数: 7881 | 3 现在谁还搞assert property (@(posedge clk)
都搞那种没用的software algo。。。 |
z*******r
发帖数: 19 | |
