c********0
发帖数: 104 | 1 Hi, We have an openning for digital design engineer.
Requirements:
1) Familiar with digital sub module designs
2) Familiar with Verilog
3) Familiar with systemVerilog assertion
4) Familiar with digital design flow and tools, such as design compiler,
primetime
5) Familiar with Verilog simulation tools and debug tools.
Please send your resume to c*********[email protected]. Thank you
Cheney |
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