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发帖数: 555 | 1 Introduction
In this article, which our team will regularly update, we will maintain a
growing list of information pertaining to upcoming hardware releases based
on leaks and official announcements as we spot them. There will obviously be
a ton of rumors on unreleased hardware, and it is our goal to—based on our
years of industry experience—exclude the crazy ones. In addition to these
upcoming hardware release news, we will regularly adjust the structure of
this article to better organize information. Each time an important change
is made to this article, it will re-appear on our front page with a "new"
banner, and the additions will be documented in the forum comments thread.
This article will not leak information we signed an NDA for.
Feel free to share your opinions and tips in the forum comments thread and
subscribe to the same thread for updates.
Last Update (17th Jan):
Removed "new Ryzen 2000 models"; these were launched as OEM-only
Added Ryzen 3000U Series APUs
Updated AMD Zen 2 / Ryzen 3000
Updated Intel Core "KF" SKUs
Added Intel "Lakefield" heterogenous processor
Added Intel Willow Cove and Golden Cove Cores
Added NVIDIA GeForce GTX 1660 Ti and TU116
RTX 2060 and GTX 1060 GDDR5X are now launched
Updated RTX 2060
Updated RTX 2050
Updated NVIDIA RTX Turing Mobile
Added AMD Radeon VII
Removed launched Polaris 30 / RX 590
Older Updates
Processors
AMD Ryzen 3000U series APUs [launched]
Based on existing 14 nm "Raven Ridge" IP, neither 7 nm nor Zen 2
Codename "Picasso"
Ryzen 3 3100U is a 2-core/4-thread SKU
Ryzen 3 3200U is essentially a Ryzen 5 2500U with 100 MHz CPU speed-bump
Ryzen 5 3500U essentially a Ryzen 7 2700U with 100 MHz CPU speed-bump
Sources
AMD Zen 2 / Ryzen 3000 [updated]
Release Date: sample in 2018, launch in 2019
Client-segment Ryzen 3000-series launch probably at Computex 2019 (June)
7 nm production process at TSMC
7 nm brings 2x density, 1/2 power (at same performance), or 1.25x
performance (at same power)
Claims better performance/watt than Intel 10 nm
Floating point unit doubled to 256-bit
AMD South Korea confirmed the existence of Ryzen 5 3600X and Ryzen 7 3700X (
contest asking people to correctly guess the Cinebench scores of the two
chips)
EPYC SKUs come with up to 64 cores, using four to eight 7 nm CPU dies (each
has 8 cores)
The CPU dies are connected to a central IO die, which is still made on 14 nm
L3 Cache per CCX doubled (16x 16 MB on 8-chiplet 64-core Rome CPU)
Adds support for PCI-Express 4.0 (128 lanes total: 96-lanes on EPYC from the
CPU + 32 from the Southbridge)
EPYC parts use an 8-channel DDR4 memory interface
Major update to the microarchitecture, including IPC improvements
New front end with improved branch-predictor, faster instruction prefetch,
large L1 and L2 cache
Codename: Matisse (CPU), Picasso (APU w/ IGP)
Hardening against Meltdown/Spectre (through architecture)
Adds new instructions: Cache Line Write Back (CLWB), Read Processor ID (
RDPID), and Write Back and Do Not Invalidate Cache (WBNOINVD)
13% IPC gain over Zen+, 16% over Zen 1
Some applications are 29% faster than Zen 1
Continues to use socket AM4
Tape-out: end of 2018
Socket AM4 package a multi-chip module of 2-3 dies, an I/O controller die
and 1 or 2 eight-core "Zen 2" CPU complex dies, each talking to the other
over InfinityFabric.
AMD CES 2019 demo with 8-core/16-thread Ryzen 3000 AM4 prototype beats Core
i9-9900K in multi-threaded Cinebench.
Sources
AMD Zen 3
Release Date: 2020
Codename: Vermeer (CPU), Renoire (APU w/ IGP), Dali (value APU w/ IGP)
Server platform codename "Milan"
New process tech: 7 nm+
New CPU core
Continues to use socket AM4
Sources
AMD Zen 4
Release Date: Unknown
"In Design" as of Nov 2018
Sources
AMD Threadripper 3rd Gen
Release Date: 2019
Codename: Castle Peak
New process tech
New CPU core
Stays on socket TR4
Sources
Intel 9th Gen Core KF SKUs [updated]
To release throughout Q1-2019, starting late-January
Includes Core i7-9700KF, Core i5-9600KF, and Core i3-9350KF unlocked CPUs
Also includes locked Core i5-9400F
These SKUs essentially lack integrated graphics, either disabled or
physically absent
Slightly cheaper price point than regular models with IGP
Maximum memory amount reverted to 64 GB from 128 GB
Sources
Intel "Lakefield" Heterogenous processor [added]
Release Date: unknown
Uses 10 nanometer production process
A rendition of ARM big.LITTLE, but with Intel x86 cores
One large performance core combined with four low-power cores, and power-
gating added to the mix
Big core is Sunny Cove based, small cores are Gracemont based
Integrated Gen11 iGPU
Fully integrated chipset and network interfaces
Package designed for PoP (package over package) setups with DRAM and NAND
flash chips over Foverous packaging
Target devices include tablets and tablet+notebook convertibles
Project Athena is an industry-wide effort involving a dozen companies to
develop the next step in powerful mobile computing, rivaling the Ultrabook
development a decade ago
Sources
Intel Comet Lake
Release Date: 2019
Introduces 10-core CPUs
Uses 14 nm production process
Socket LGA1151
No significant architectural changes expected over "Coffee Lake"
Same cache hierarchy, with 256 KB per core L2 cache, and 20 MB shared L3
cache
Developed to counter AMD's Zen 2
Sources
Intel Cannon Lake
Release Date: Additional processors delayed to 2019
One mobile SKU launched in May: Core i3-8121U 2.2 GHz, no integrated
graphics
Core M3 8114Y: 1.5 GHz base, 2.2 GHz boost, 4.5 W TDP, Intel UHD iGPU
10 nanometer production process
DDR4L support
Intel is reportedly having difficulties ramping up 10 nm, which could lead
to delays
Adds AVX512 instructions (so far available only on HEDT platform, since
Skylake-X). New instructions: AVX512F, AVX512CD, AVX512DQ, AVX512BW, and
AVX512VL. New commands: AVX512_IFMA and AVX512_VBMI
Sources
Intel Cascade Lake
Release Date: Q4 2018 or Q1 2019
Server/Enterprise version of Whiskey Lake
Same microarchitecture as Coffee Lake
Still on 14 nm, using a slightly improved process
48 cores spread across two dies, using multi-chip-module
Adds support for Optane Persistent Memory
12 memory channels per CPU
88 PCI-Express lanes
Mitigations for recent Intel vulnerabilities
Deep Learning Boost (Variable Length Neural Network Instructions)
Sources
Intel Cooper Lake
Release Date: 2019
Refresh of Cascade Lake
14 nanometer production process
Uses same socket and platform
Deep Learning Boost gets additional instructions (compared to Cascade Lake):
BFLOAT16
Higher clock speeds
Sources
Intel Ice Lake
Release Date: Late 2019
Uses 10 nanometer DUV (deep-ultraviolet) process
Uses a brand-new CPU core design codenamed "Sunny Cove"
Adds AVX512 instructions (so far available only on HEDT platform, since
Skylake-X). New instructions: AVX512F, AVX512CD, AVX512DQ, AVX512BW, and
AVX512VL. New commands: AVX512_IFMA and AVX512_VBMI
20-30 broadening of various number crunching resources, wider execution
window, more AGUs
SHA-NI and Vector-AES instruction sets, up to 75% higher encryption
performance vs. "Skylake"
Integrated GPU based on new Gen11 architecture, up to 1 TFLOP/s ALU compute
performance
Integrated GPU supports DisplayPort 1.4a and DSC for 5K and 8K monitor
support
Gen11 also features tile-based rendering, one of NVIDIA's secret-sauce
features
Integrated GPU supports VESA adaptive V-sync, all AMD FreeSync-capable
monitors should work with this
Sources
Intel Willow Cove and Golden Cove Cores [added]
Release Date: 2020 and 2021
Succeeds "Sunny Cove"
Willow Cove improves on-die caches, adds more security features, and takes
advantage of 10 nm+ process improvements to increase clock speeds versus
Sunny Cove
Golden Cove will add significant single-thread (IPC) increases over Sunny
Cove, add on-die matrix multiplication hardware, improved 5G network-stack
HSP performance, and more security features than Willow Cove
Sources
New 28-core HEDT platform derived from LGA3467
Released as Xeon W-3175X, priced at $4,000, 255 W TDP, 3.1 GHz Base, 4.1 GHz
Boost
Client-segment implementation of the Skylake XCC die
No STIM
Up to 28 cores: 16-core, 24-core, 26-core, and 28-core SKUs possible
HyperThreading available
Six-channel DDR4 Memory interface, Up to 768 GB non-ECC memory
Uses new X599 chipset, new motherboards required
44 PCIe gen 3.0 lanes
Two AVX-512 FMA Units
14 nm++ process
Confirmed Motherboard: ASUS ROG Dominus Extreme
Sources
Graphics / GPUs
NVIDIA GeForce RTX 2070 Ti
Gigabyte (where "2070 Ti" originated from), now claims that this was just a
typo
Release Date: Unknown
Based on Turing TU104 (same as RTX 2080)
Faster than GTX 1070 Ti and GTX 1080
Pricing $600-650 (ie, half of RTX 2080 Ti)
Sources
NVIDIA GeForce RTX 2050 [updated]
Release Date: 2019
Based on new, smaller, chip
Sources
NVIDIA GeForce RTX 2060 [launched]
RTX 2060 launched on January 8th and features 1,920 CUDA cores, 120 TMUs, 48
ROPs, and 6 GB GDDR6 memory across 192-bit wide memory bus. Our Reviews
Possibility of more variants in the future based on memory type (GDDR6 or
GDDR5), memory size (6 GB or 4 GB)
Sources
NVIDIA GeForce GTX 1060 GDDR5X [launched]
GTX 1060 GDDR5X is now available from multiple vendors, our review of the
KFA2 GTX 1060 GDDR5X
Uses GP104 GPU (same as GTX 1070 & 1080)
1280 shaders, 80 TMUs, 48 ROPs (just like regular GTX 1060)
Sources
NVIDIA GeForce GTX 1660 Ti [added]
Based on Turing architecture, but without RTX technology
Based on new 12 nm TU116 silicon
Features 1,536 CUDA cores based on Turing architecture, and 192 tensor cores
to accelerate DLSS
Modified streaming multiprocessor design lacks RT cores but features tensor
cores
6 GB of GDDR6 memory across a 192-bit bus.
Possible spring-summer release at a sub-$300 price-point, to succeed GTX
1060 6 GB
Sources
NVIDIA Volta
Architecture launched with $3000 Titan V
Seems to be a dead end, now with Turing being the newer architecture and
already released
NVIDIA Ampere
Release Date: 2018
Possibly scrapped due to end of mining boom
Sources
NVIDIA Turing Mobile / RTX 20-Series Mobility [updated]
Release Date: Q1 2019
Officially announced at CES 2019
GeForce RTX 2080 Mobility Max-Q, based on TU104M
GeForce RTX 2070 Mobility Max-Q
GeForce RTX 2060 Ti Mobility
GeForce RTX 2060 Mobility
GeForce RTX 2050 Ti Mobility
GeForce RTX 2050 Mobility
Sources
AMD Vega 20
Machine learning version announced in Nov 2018, called "Radeon Instinct MI60
" and MI50, shipping in Q4 2018
Questionable whether consumer product will be released
New MCM with 7 nm GPU die with 4096-bit HBM2 interface
13.2 billion transistors, 331 mm2
Four HBM2 stacks, up to 32 GB memory, up to 1 TB/s memory bandwidth
1.25x higher performance (at same power) or 50% lower power (at same
frequency)
PCI-Express gen 4.0 bus interface
Supports hardware virtualization
7.4 TFLOPs FP64, 14.7 TFLOPs FP32, 118 TOPS INT4
Up to 2x higher density
Supports FP64 and FP32
Adds machine learning operations for Training and Inference
End-to-end ECC protection
Could feature a new interconnect, to compete with NVIDIA NVLink
Sources
AMD Radeon VII [added]
Release Date: Announced at CES 2019, available Feb 7, 2019
Priced at USD $699
Game bundle: Devil May Cry 5, Resident Evil 2 and The Division 2.
AMD claims gaming performance to rival GeForce RTX 2080
Gaming graphics card based on "Vega II" architecture and 7 nm "Vega 20"
silicon
3,840 stream processors, 240 TMUs, 64 ROPs
4096-bit HBM2 interface
16 GB HBM2 memory
Limited FP64 compute abilities, typical of client-segment
Reference-design only, no custom-design cards
Cards sold both directly from AMD, and through add-in-board partners, which
sell reference design with their own stickers
Sources
AMD MI-NEXT
Release Date: Unknown
Successor to Vega 20
Sources
AMD Navi
Release Date: 2019, probably H2
TSMC, 7 nm
Sources
AMD Arcturus
Release Date: 2020
TSMC, 7 nm+
Sources
Intel XE Discrete Graphics
First Intel Discrete GPU since ill-fated Larrabee
New architecture built from the ground up, and not an upscale of Gen11
Double-digit TFLOP/s scaling all the way up to 0.1+ PFLOP/s
Targeting a wide segment of markets, including consumer (client-segment)
graphics, enthusiast-segment, and data-center compute
Sources
Intel Discrete GPU / Arctic Sound
Release Date: 2020
Intel will hold an event in December 2018, providing more details
Advanced management for power and clocks
Test chip: 8x8 mm2 die area, 1.54B transistors, 14 nm, 50-400 MHz clock, EUs
at 2x clock if needed
Raja Koduri who left AMD in late 2017 is somehow involved
Confirmed to support VESA Adaptive Sync
Sources
Intel Jupiter Sound
Release Date: 2022
Discrete GPU
Produced on 10 nanometer production process
Successor to Arctic Sound
Sources
Chipsets
Intel B365 Express Chipset [launched]
Release Date: late 2018
Replaces B360 Express from the product stack
Essentially a re-branded Q170 or H170 PCH built on older 22 nm HKMG+ process
Uses older ME version 11 compared to B360 which uses ME version 12
No integrated USB 3.1 gen 2 controller
More downstream PCIe lanes: 20 gen 3.0 lanes compared to just 12 from B360
Six SATA 6 Gbps ports
Platform drivers for Windows 7
Sources
Intel X399
Release Date: unknown
Supports Coffee Lake-X and Cannon Lake-X
Sources
Intel X599
Release Date: Unknown
Supports new Intel 28-core HEDT platform
New motherboards, with new socket: LGA3647
Based on C629 Server Chipset
6-channel memory
48 PCIe lanes
Sources
Intel Z399
Release Date: Unknown
New HEDT chipset
Sibling chipset to X599
Socket LGA2066
For 20- and 22-core CPUs
Works with existing Skylake-X LCC and HCC chips
Sources
AMD X499 Chipset
Release Date: Q1 2019
Supports Threadripper
Unknown changes
Sources
AMD Z490 Chipset
Unknown release date
Increases number of downstream PCIe lanes by adding four PCIe Gen 3 lanes on
top of the existing eight PCIe Gen 2 lanes
Other features identical to X470
Sources
Memory
DDR5 System Memory
Release Date: Late 2019/2020
JEDEC standard not fully complete yet, expected for summer 2018
Demo'd in May 2018 by Micron: DDR5-4400
Samsung 16 Gb DDR5 DRAM developed since February 2018
Samsung has completed functional testing and validation of a LPDDR5
prototype: 10 nm class, 8 Gbit, final clocks: DDR5-5500 and DDR5-6400
SK Hynix has 16 Gb DDR5-5200 samples ready, 1.1 V, mass production expected
2020
4800 - 6400 Mbps
Expected to be produced using 7 nm technologies
64-bit link at 1.1 V
Voltage regulators on the DIMM modules
Sources
HBM3 Graphics Memory
Release Date: Not before 2019
Double the memory bandwidth per stack (4000 Gbps expected)
Expected to be produced using 7 nm technologies
Sources
Other
Hynix 4D NAND
Release Date: H1 2019
Developed by SK Hynix
Sampling in Q4 2018
Reduces chip physical size, while increasing capacity at the same time
Supports TLC and QLC
30% higher write and 25% higher read performance
1.2 V
1st generation: 96 stacks, 1.2 Gbps per pin, 512 Gbit TLC
128 stacks in development, scales up to 512 stacks
Sources
Toshiba XL-Flash
Developed by Toshiba
Uses existing SLC flash technology to improve latencies
1/10th the read latency of TLC
Good for random IOPS and better QoS at shallow queue depth
Can combine SLC and TLC/QLC for tiered, cost-optimized storage
Intel Optane memory competitor
Sources
PCI-Express 4.0
Specification released in late 2017
16 GT/s bandwidth per lane, per direction (2x the bandwidth of PCIe 3.0)
Reduced latency
Lane margining
I/O virtualization capabilities
Will be supported by AMD Zen 2 and Vega 20 (Radeon Instinct MI60 & MI50)
Sources
PCI-Express 5.0
Release Date: Q1 2019
32 GT/s bandwidth per lane, per direction (4x the bandwidth of PCIe 3.0)
128/130 bit encoding (= 1.5% overhead)
Physical connector targeted to be backward compatible
Sources |
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