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EE版 - EE本科 CS master 电路设计 求内推
相关主题
subthreshold slope <60mV/decade?电路设计不出啊,老板又去度假了,擦了!
DC offset of integrator求问:怎么高速读出 sram 里的数据?
Vgs < Vth 的bias ?为啥单片机还要弄个os
subthreshold IC 的优点和缺点有哪些?最后再求一次ASIC/VLSI数字电路的内推!小弟必知恩图报!
求ASYNC VLSI 科普any documentation software for AVR assembly?
有关Asynchronous FIFO和Dual port SRAM 请教几个interview问题
变频发电机和恒频发电机的优缺点AVR 还是 PIC
请教两个synchronizer的问题用什么设备可以让电脑输出SPI信号
相关话题的讨论汇总
话题: designed话题: september话题: qdi话题: spi
进入EE版参与讨论
1 (共1页)
c***4
发帖数: 57
1
intel已经找到同学内推了
还投了broadcom和qualcomm的几个职位
求内推
主要经历
Power Gating QDI Stateless Systems
September 2010 – Present
Quantified reset timing assumption and proposed an algorithm to shorten the
wake-up latency of power-gated QDI systems
Simple Asynchronous Microprocess (SAM)
September 2011 – December 2011
Described SAM using Communicating Hardware Processes (CHP) and decomposed it
into logic gates
QDI SPI Master Controller
May 2012 – September 2012
Designed a QDI Serial Peripheral Interface (SPI) master controller for
serial data communication between a QDI AVR and a SPI FLASH memory
Designed Asynchronous Subthreshold Adders and FIFOs
July 2008 – June 2009
Designed a Frequency-Response-Masking Based Filter Bank
July 2009 – June 2010
Ultra-low power frequency-response-masking based filter bank for implantable
biomedical devices
Designed a 6-bit FLASH ADC
September 2007 – January 2008
Designed an Asynchronous 8051
September 2007 – May 2008
Designed an asynchronous 8051 using Balsa and synthesized layout using SOC_
Encounter.
谢谢了
s***d
发帖数: 15421
2
你这背景应该做eda去。
c***4
发帖数: 57
3
大哥能具体说说么
但是 我好像都是用软件design具体的电路
没有开发软件本身啊
1 (共1页)
进入EE版参与讨论
相关主题
用什么设备可以让电脑输出SPI信号求ASYNC VLSI 科普
帮我表弟问问单片机的问题有关Asynchronous FIFO和Dual port SRAM
请教Verilog 实现SPI的问题变频发电机和恒频发电机的优缺点
[救命]关于一个pcb上用2个crystal for clock input请教两个synchronizer的问题
subthreshold slope <60mV/decade?电路设计不出啊,老板又去度假了,擦了!
DC offset of integrator求问:怎么高速读出 sram 里的数据?
Vgs < Vth 的bias ?为啥单片机还要弄个os
subthreshold IC 的优点和缺点有哪些?最后再求一次ASIC/VLSI数字电路的内推!小弟必知恩图报!
相关话题的讨论汇总
话题: designed话题: september话题: qdi话题: spi