s*****g
发帖数: 8 | 1 There is an immediate job opening for ASIC design verification engineer in
our group. The location is in Santa Clara, CA.
Requirements include:
- MS or PhD in EE, CompE, or equivalent
- Demonstrated skills in digital circuit design and solid understanding of
Verilog or VHDL, knowledge of SystemVerilog is a plus
- Demonstrated skills in ASIC/FPGA design, simulation, and synthesis
- Knowledge of object-oriented programming, such as C++ and Java
If interested, please send resume to g****[email protected]
Good luck! |
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