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发帖数: 428 | 1 假如有某个frequency的clock。
Block1: 希望成产生从100MHz到700MHz的clock,比如说100, 105, 110, 115, 120,
..., 695, 700. digital来控制。
Block2:假如生成了345MHz的clock,想再把它分成32个phase，就是把一个cycle平分
成32分
请问Block1和Block2如何来实现呢?大概需要用到什么？大家给点建议也行：）
多谢！！ | h********t
发帖数: 555 | 2 Block 1, you can use a relaxation oscillator. its frequency is depending on
RC. You can switch in/out capacitors digitally. The problem is you need to
trim resistor to take care of process variation, and the resistor needs to
have almost zero temperature coefficient, if you really want a precise
output frequency and also want it stable over temperature. In most design, I
doubt such requirement is really necessary. If you already have an external
clock, you can probably use PLL to do so. it is m | a********e
发帖数: 381 | 3 找个 digital synthesier的datasheet看看 |
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