j***u
发帖数: 26 | 1 I designed an integrator, it is actually a low pass filter, a simple one
stage differential amplifier with one terminal input short to the output and
connected to a capacitor. In this case, the input is a signal, the output
would be the input average voltage. All the transistors work in the weak
inversion. The integrator has a tail current of 100pA. The transistor were
sized to have a DC offset of 5mV, that means the output is 5mV apart from
the input DC level. However, when I tested this integr |
g*******r
发帖数: 140 | 2 50mV is really a big number regarding the offset..
"the transistor is sized to have a DC offset of 5mV", you mean you just use
unequal input pair or current mirror pair to get a build-in offset?
and
as
this
【在 j***u 的大作中提到】
: I designed an integrator, it is actually a low pass filter, a simple one
: stage differential amplifier with one terminal input short to the output and
: connected to a capacitor. In this case, the input is a signal, the output
: would be the input average voltage. All the transistors work in the weak
: inversion. The integrator has a tail current of 100pA. The transistor were
: sized to have a DC offset of 5mV, that means the output is 5mV apart from
: the input DC level. However, when I tested this integr
|
j***u
发帖数: 26 | 3 the transistor pair has the same size. I estimate the offset according to
the mismatch of transistors |
j***u
发帖数: 26 | 4 I wonder what kind of cap normally is used for the filters? This big dc
offset comes from where? I really have no idea |
g*******r
发帖数: 140 | 5 Are you using mos cap for area saving? I have no experiences on using mos-
cap for ultra-low power filter design. Mos cap is not linear and there are
more gate/substrate leakage, especially for short-channel process.
From your informations, the DC gain of the inegrator should be small to
create 5mV dc voltage offset. Your dc current is quite small (100p) and all
transistors are in subthreshold? If you want to operate them in subthreshold
, I suggest to make a large |Vgs-Vth| value, otherwise the
【在 j***u 的大作中提到】
: I wonder what kind of cap normally is used for the filters? This big dc
: offset comes from where? I really have no idea
|
j***u
发帖数: 26 | 6 All transistors work in subthreshold. The simulation results show the dc
offset is less than 1mV. 5mV offset is calculated according to the Vth
variance supplied by the process. I haven't run the corner simulations. But
I test serveral chips, they gave me similar DC offset.
So you think, 100pA tail current should not be the reason to cause this big
DC offset? The leakage of transistors is neglectable comparing to 100pA,
right? |
j***u
发帖数: 26 | 7 All transistors work in subthreshold. The simulation results show the dc
offset is less than 1mV. 5mV offset is calculated according to the Vth
variance supplied by the process. I haven't run the corner simulations. But
I test serveral chips, they gave me similar DC offset.
So you think, 100pA tail current should not be the reason to cause this big
DC offset? The leakage of transistors is neglectable comparing to 100pA,
right? |
g*******r
发帖数: 140 | 8 What kind of process do you use? According to my experience, for 0.35um, the
100pA should be OK.
I think the 100pA tail current is not the cause.
But
big
【在 j***u 的大作中提到】
: All transistors work in subthreshold. The simulation results show the dc
: offset is less than 1mV. 5mV offset is calculated according to the Vth
: variance supplied by the process. I haven't run the corner simulations. But
: I test serveral chips, they gave me similar DC offset.
: So you think, 100pA tail current should not be the reason to cause this big
: DC offset? The leakage of transistors is neglectable comparing to 100pA,
: right?
|
g*******r
发帖数: 140 | 9 and also you use probe with very high impedance to test the circuit?
the
【在 g*******r 的大作中提到】
: What kind of process do you use? According to my experience, for 0.35um, the
: 100pA should be OK.
: I think the 100pA tail current is not the cause.
:
: But
: big
|
c*******e
发帖数: 18 | 10 Did you check the accuracy of the spice model for trasistors working in
subthreshold region? |
|
|
j***u
发帖数: 26 | 11 So glad to hear this. Then the DC offset should be caused by the MOSCAP,
which unbalance the differential pair in the layout. By the way, i am using
0.25um process
the
【在 g*******r 的大作中提到】
: What kind of process do you use? According to my experience, for 0.35um, the
: 100pA should be OK.
: I think the 100pA tail current is not the cause.
:
: But
: big
|
j***u
发帖数: 26 | 12 I use the oscilloscope to monitor the output. It should be high impedance.
【在 g*******r 的大作中提到】
: and also you use probe with very high impedance to test the circuit?
:
: the
|
j***u
发帖数: 26 | 13 it cannot be caused by accuracy of weak inversion. Because i also designed a
comparator with offset of 5mV and the measurement showed the comparator
works as designed.
【在 c*******e 的大作中提到】
: Did you check the accuracy of the spice model for trasistors working in
: subthreshold region?
|
j***u
发帖数: 26 | 14 Hi, eejob, thanks for your reply. But I cannot find your post, so i cannot
answer your questions. I even cannot reply your short message. could you
please post again? |
j***u
发帖数: 26 | 15 The tail current of the comparator is 1.2nA. |
j***u
发帖数: 26 | 16 Thanks eejob for your reply. In fact, I did have a buffer connecting between
the integrator output and ESD pad. So the leakage of ESD should not be an
issue. And the buffer offset has been considered when measurement. Well, the
integrator will be used in a large system. I just hope this offset is not
caused by the leakage of the transistors due to such small tail current. I
will make the measurement again using oscilloscope to make sure high
impedance mode. Really thanks for your reply.
By the w |
