One digital IC design/verification engineer openning - Classified版

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Classified版 - One digital IC design/verification engineer openning

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话题: ic话题: digital

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(共1页)

c********0
发帖数: 104

Requirements:
1) 诚实，头脑清晰
2) BSEE背景
3) 熟悉digital IC design/verification flow
4) 熟练运用verilog, 会SystemVerilog更好
5) 会Perl，C-shell等
Please send your resume to c*********[email protected]. Thanks.

(共1页)

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● 恳求工作内推: Electrical and Computer Engineering方向	● 【供求】Sr SW Engineer Contract Position
● 最后一次恳求工作推荐: EE--------Digital Logic Design/VLSI/	● BRCM hardware application enginner opening
● 【湾区】继续需要一个EECS方向的intern，站内联系 (转载)	● 急聘C++ Software Engineer (San Jose, CA)

相关话题的讨论汇总
话题: ic话题: digital

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